Hot answers tagged

4

12 MHz is the default and only one that works in hardware mode so the PLL settings do not need to be altered.


3

The S/PDIF data rate is 3.072 Mbps max (@ 48 kHz sample rate), and with biphase encoding, that means an analog bandwidth that's also around 3 MHz. At these frequencies, and given the maximum cable length of ~10m, the small impedance "bump" created by a TRS connector is really not going to cause any noticeable problem.


2

R1 provides hysteresis to the comparator so that it will not "dither" when the voltage is close to the threshold. https://en.wikipedia.org/wiki/Comparator#Hysteresis


2

This was actually quite commonly done back in the day. In fact, some soundcards had a little auto-detect feature where if you plugged in a mono 3.5 mm plug, they would output S/PDIF, while if you plugged in a stereo one they output analog. Likely the switching was actually implemented in driver software, but it was fairly transparent to the user - ...


2

Best solution in terms of achievable throughput would probably be a CPLD or small FPGA. If that's not reasonable, then I would recommend using frequency modulation. Use a timer/counter to transmit and another one to receive. Perhaps have 3 different frequencies, one for idle, one for high, and one for low. Transmit complete cycles of various widths on ...


1

The other answers missed the obvious, so here we go. WM8804's SPDIF output uses LVCMOS 3.3V levels. Then, you use TC7W04, a 74HC-equivalent chip powered from 5V. Its inputs are not really compatible with LVCMOS 3.3V, which is why it does not work. Then we have a resistor divider which brings the output level down to +/- 0.5V. To output +/- 0.5V levels, ...


1

1) It is a CMOS inverter, it works poorly when supply is 5V but signal input is not 5V but 3.3V. Another thing could be output drive strength. It is also not ideal to parallel outputs - at least not directly without series resistors. 72 ohms is of course not perfect but within 5% so that should not be an issue. 2) No, not really. But the resistances would ...


1

Yes, the "body" pins must be grounded in order to ground the shield of the coax cable.


1

The BC127 module outputs a 3.3V logic level SPDIF signal that can be connected to multiple logic level devices, but a driver circuit is needed to properly drive a 75 ohm 0.5Vpp coaxial output interface. Connecting the logic level output directly to coaxial connector won't work and it can't drive a standard 75 ohm coaxial input.


1

They are intended to bias the inverter into operation as a linear amplifier, but this is likely to result in high frequency oscillation unless you use an unbuffered inverter such as the 74HCU04. When it works, the input sits at about midway between the logic levels of Vih and Vil or about 1.4V in this case. Since the input is AC-coupled that doesn't matter ...


1

Digging some more, I found this other electronics.SE post that answers my question (in passing, but still explicitly). The answer being: yes, the WM8804 does as indicated in the datasheet, Figure 15.


1

Reposting the answer I put in a comment: I want to use a Cirrus Logic WM8804 to convert the I2S data to S/PDIF @ 44.1khz (please ignore the fact that the BC127 can output S/PDIF -- I need both digital audio formats) Wouldn't it be simpler to have your bluetooth module output SPDIF, then use the WM8804 to decode this into I2S? You'd get both SPDIF and I2S ...


1

If I need a stable external clock source, and I'm not concerned about price. I usually use an XO CMOS output oscillator. Supply it with 3.3V and it gives you a clock out for the MCLK (in the datahseet the MCLK timing indicates that the MCLK can be set on Xin pin) . There are many different frequencies available Source: https://www.digikey.com/products/en/...


1

The logic gates have a "U" in their name, which stands for "unbuffered". The SN74LVC1GU04 datasheet says: 8.3.6 Unbuffered Logic A standard CMOS logic function typically consists of at least three stages: the input inverter, the logic function, and the output inverter. Some devices have multiple stages at the input or output for various reasons. An ...


1

Check inside the CD player, follow the SPDIF output trace and probe around. Most likely you will find the SPDIF output comes from the big CD decoding chip, it will probably be 3.3V in level, and go through a 75R resistor and maybe a capacitor and some other resistors. Find the point before the resistors and caps where you have a nice logic level waveform, ...


1

The datasheet suggests that the TORX device cannot drive a 430 ohm load (see the Abs Max Iout) though it's overall pretty vague (I can't see the specified load for the VOut specification). Whether you need 2 stages of inversion is another matter - the S/P-DIF format comes from AES/EBU which was designed to work equally well inverted or not. So I believe you ...


1

The schematic shows a TORX173/176 which is confusing. It also makes it look like the TORX modules have more than 3 pins yet these modules have only 3 pins: vdd, data and gnd, also confusing ! I believe the TORX modules already have some inverter like circuits build-in so adding inverters (the 74HCU04) seems somewhat pointless to me. I build such a thing ...


Only top voted, non community-wiki answers of a minimum length are eligible