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There are 7+ mainstream STM32F0 MCUs with 8 USART interfaces. There are several high performance STM32F4/F7 chips with 4 USART + 6 UART (for 10 total) interfaces, and three dozen chips with 4 USART + 4 UART (for 8 total). I am pretty sure you can find similar options from other manufacturers if you stop looking for DIP package. The adapters from LQFP to DIP ...


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A number of SPI slaves can be connected in one of two configurations: Single Slave-Select daisy-chained Here the entire SPI bus is treated as one big shift register and the master must know the order of devices in the bus chain and their respective register widths. It is also necessary to write all devices at the same time in the same bus transaction. ...


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Yes, the length of the wires used for SPI can affect the functionality. Longer wires give more capacitance, which is harder to switch high and low at high data rates. But longer wires will still conduct current, and a continuity test is at low frequency, so something else is going on herre. Try measuring the actual resistance of the connecting wires instead ...


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What is being proposed is to gate the SPI clock with GPIO pins. Looks like ATMega328 SPI controller stops the clock between transfers, so it’s practical to use clock gating. GPIO can be used to direct the clock to the appropriate device, with software changing the GPIO between transfers. This ADC uses clock-idle low (CPOL=0), so the gating logic needs to ...


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I think I may have found the answer, after some more digging. The RF chip seems to be PL1167. Going through the register datasheet, I can see that register 0x23 is power management (first message that gets sent in my remote), 0x34 is FIFO pointer, 0x32 is FIFO data, 0x07 is TX enable, which coincides very well with what I'm seeing on the traces. The ...


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So I tried some more stuff. Eventually I tried to read the REMS using an arduino that worked after sending a dummy byte while trying to retrieve data. I now tried the same with the TI board and it returned data. Updated function for retrieving the REMS is now: //BLS_CODE_MDID = 0x90 uint8_t wbuf[] = { BLS_CODE_MDID, 0xFF, 0xFF, 0x00 }; ...


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1m is not that much. Even in noisy environment good shielding and low speed should be enough to achieve reliable communication. That is, unless you are going to run this thing next to aircraft radar or ark welder. A simple solution would be to use shielded CAT5/6 cable. One twisted pair would be SCK+GND, another MOSI+GND, and the remaining 4 can be used for ...


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You don't show the erase function, but depending on which size of erase you send, it may take more than 2000ms to complete. Full chip erase can take 10 seconds. You should check the flash status register if it says it's busy or not. Therefore it may not be ready for the first read command. And you don't enable write latch before byte write, so it will not ...


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A first step to understanding this reading issue is to study the NAND Flash connections with an oscilloscope. Do this first without the BusPirate connected. With the circuit board in the same state as when you were trying to read see if the circuit board's other electronics is trying to make accesses to the NAND Flash. If there are other transactions then be ...


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