There is a dedicated pin that defines whether there is a pull-up on all pins during configuration or not: HSWAPEN.
The "Spartan-6 FPGA Configuration User Guide" UG380 contains all the details in plain text.
The resistors are added because the designer has no clue about how to design the circuit. They only make the circuit worse, limiting the data rate. 3k3 is far too high value to allow for useful SPI clock rates, so they are not simply for EMI noise reduction.
The most propable reason the resistors are drawn in the circuit is that the designer appears to think ...
Since SPI is a bus, the bus is shared between all connected components. With a single bus, the communication at any time is limited to a single pair of SPI master and slave. It's not possible to communicate with two slaves concurrently.
A single bus will have a lower transmission rate compared to two or more SPI buses working concurrently.
However, if you ...
The approach is:
Configure SPI to use software slave select (bit SSM on SPI_CR1 register)
Trigger the slave select (internally) by setting and clearing the internal slave select (bit SSI on SPI_CR1 register)
If you like to, you can permanently set the internal slave select. The SPI peripheral will send and receive data as long as SSI bit is set, driven by ...
If some (insert semiconductor corporation) develops a process of increasing the density of FRAM, it could replace DRAM.
While marginally slower than SRAM, this could upend the DRAM industry for being a cheaper, more performant alternative to our main memory in PC's, DRAM.
Considering the widening CPU to Memory Speed/Bandwidth gap problem - FRAM as I see it ...