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12

SPI is not some rigorously defined standard, but more of a de-facto thing. Normally the SPI clock is only active when the master wants to send/receive data. In general a SPI transaction looks like. The master asserts chip select The master clocks through the desired number of data bits. Normally data is clocked out on one edge and clocked in on the other ...


8

You must control the applicable enable pin of the Si8641. If you examine the truth table in the Si8641 data sheet, you will see that the only situations where the output is High-Z are those where the governing enable input is low. It would appear that EN1 governs A4 which you are using for MISO, while EN2 governs the other channels which you are using in the ...


7

The SPI clock is only active while the chip select is low, yes. As correctly stated in the comment, if there's no transmission active, the clock will stay idle even if the chip select is low. The idle state of the clock (high or low) depends on the chosen SPI mode https://www.analog.com/media/en/analog-dialogue/volume-52/number-3/introduction-to-spi-...


7

don't care or better: any state allowed


6

Yes, in theory "any GPIO" would do; this is called "software chip select" But many SPI host engines also offer a "hardware chip select" option to control a dedicated pin from the SPI engine itself, which is a hair more efficient and keeps the software simpler. (It might also tie in with alternate uses of a synchronous serial ...


5

AVR microcontrollers (and most modern ┬ÁC) contain special hardware specifically for programming directly using a combination of the SPI port (called ISP for this special case) and the reset pin. This is a very convenient feature because you don't need to worry about bootloaders or memory offsets or anything else. You can program the chips separately or ...


5

Question How come my MCP23S17 GPIO extender gets very hot and goes crazy? / to continue, ... Answer Part 1 - Test setup I would suggest to start with a smaller version of the user requirements. For example, instead of making things very flexible, any pin can be input or output, you can in the testing phase, let 8 pins input only, and another pins output ...


4

Hard to tell a lot without the schematic that you used to drive the net list into the layout package. You did use a schematic to derive the net list did you not?? Things that are obvious problems. Distributing the 5V rail around the board on an 8 mil trace is not good. Your prototype has a lot more copper than this and a bus bar in the plug board. No bulk ...


4

No, for the distances you need and the noisy environment you describe plain I2C or SPI will not be suitable. This problem has been essentially solved. There are communications protocols and standards that are common in industrial environments. Search for MODBUS to see one example.


4

Measuring with a scope is an art. It is not so much if your probes are grounded but more where they are grounded. Noise also greatly depends on PCB layout and the drive strength. Think if it like two person side by side: You hear the one better over the other if he shouts louder. Back to your signals: Circle : That coincides with the first data bit. ...


4

FLASH is cheap and provides lot of memory, but comes with the cost of sector erase. So you might want to use EEPROM instead. Of course it is possible to overcome this flash limitation with some clever software, which tracks the bits and bytes with a journal (i.e. you don't overwrite a byte value but write a new copy of it and note in the journal that the ...


4

Question The OP is testing MCP3008 with SPI speed 1.35MHz, and found results inaccurate. How come? Answer Update 2020aug17hkt2136 MCP3008 and MCP3208 Programming Notes Now that all basic MCP3201 functions have been tested OK, it is time to move to MCP3008 and MCP3208, both of which are more complicated that MCP3201 (Note 1). Some differences are listed ...


4

SPI slaves need a dedicated CS input pin, as it controls the hardware of SPI peripheral to either receive or ignore transmissions on bus. SPI masters typically can use any GPIO pin to control which slave is active, but if SPI master has a overly complex SPI peripheral that supports hardware CS timing control, then it is usually a dedicated CS output pin.


3

I am trying to figure out how to simultaneously update different values to them. LDAC appears to be the pin that simultaneously loads all DACs: - You just need to ensure that the channels you want to be synchronous are configured to be synchronous: - NOT TO BE CONFUSED WITH BROADCAST MODE:


3

There is no difference. The CS is always from master to slave, as master is the one that generates the clock, and slave always listens for the clock (and it basically is gated by the CS). Basically when the master transmits a byte to slave, it also receives a byte from the slave. If you want the master to receive data from slave, the slave must set the ...


3

Read the Wikipedia article on sampling (the article focuses on conversion of analog to digital, you perform opposite converting digital samples to set of dots comprising the wave). Then take a piece of paper (or some drawing application software on your PC) and draw the period of the sine wave with timing on the X axis. Then divide the drawn sine wave onto ...


3

There are 7+ mainstream STM32F0 MCUs with 8 USART interfaces. There are several high performance STM32F4/F7 chips with 4 USART + 6 UART (for 10 total) interfaces, and three dozen chips with 4 USART + 4 UART (for 8 total). I am pretty sure you can find similar options from other manufacturers if you stop looking for DIP package. The adapters from LQFP to DIP ...


3

There is no SPI standard, so the Clock Polarity (CPOL) and Clock Phase (CPHA) selection bits do not need to map to modes 0-3 in any standard way. Sometimes the mode selection bits have different names so what you read about modes for one device does not apply to another device. The point is, when you want to communicate SPI between two chips, you need to ...


3

The devices are not "daisy chained" in an I2C setup. The total number of devices depends on the capacitive load on the bus. Each device, and it's associated traces, add capacitive load. Look at your devices datasheets for how much load each device will tolerate. You'll have to do some math and know something about your PCB layout if you really wanna ...


3

Data is clocked out of MOSI and into MISO when the clock is active, it's only driven when CS is low and there's a transaction happening.


3

The remainder will alwas be the same, but if it is always zero or something elsr depends on the exact CRC algorithm, namely the "final xor". If you have to write for example written 10 bytes of data and have calculated 2 bytes of CRC from that data, you write 12 bytes to the memory. When you read if back, you read all 12 bytes, calculate the CRC ...


3

ADXL345 Datasheet. The most interesting section is on the FIFO. See page 21: The ADXL345 contains technology for an embedded memory management system with 32-level FIFO that can be used to minimize host processor burden. This buffer has four modes: bypass, FIFO, stream, and trigger (see FIFO Modes) It sounds like you should set the FIFO mode to "...


2

We found the problem which is we did not connect VDD_USB to VDD. Because PA11 and PA12 pins can be used as I/O only if VDD_USB pin is supplied between VDD_min and VDD_max.


2

These pins can have any number of uses. Sometimes they enable internal test modes or other funky connections and can cause malfunctioning of the device In one possible case given the information provided, they may be binning dual-die devices to single die when there is a failure or defect in one die instead of scrapping all together. This may leave some ...


2

I was running into a similar issue and after days of research and debugging, I noticed a trend that everyone who was having this issue configured their SPI as RX only. When I changed my SPI to TX RX mode the issue was magically solved. I'm not sure what could cause this, but it seems like a bug on ST's end, either as part of the HAL library, or as part of ...


2

I know it's been quite old but, I come across the same situation when I use MPU9250 spi with long wire, and read Ak8963 by the MPU9250 Aux I2C. Oscilloscope on SPI SCLK and Aux SCL shows that when there is a SPI reading and I2C reading happen at the same time, the I2C would hang and halt, I can see crosstalk spikes on I2C signal whenever there is SPI CLK ...


2

A first step to understanding this reading issue is to study the NAND Flash connections with an oscilloscope. Do this first without the BusPirate connected. With the circuit board in the same state as when you were trying to read see if the circuit board's other electronics is trying to make accesses to the NAND Flash. If there are other transactions then be ...


2

A number of SPI slaves can be connected in one of two configurations: Single Slave-Select daisy-chained Here the entire SPI bus is treated as one big shift register and the master must know the order of devices in the bus chain and their respective register widths. It is also necessary to write all devices at the same time in the same bus transaction. ...


2

I think I may have found the answer, after some more digging. The RF chip seems to be PL1167. Going through the register datasheet, I can see that register 0x23 is power management (first message that gets sent in my remote), 0x34 is FIFO pointer, 0x32 is FIFO data, 0x07 is TX enable, which coincides very well with what I'm seeing on the traces. The ...


2

Yes, the length of the wires used for SPI can affect the functionality. Longer wires give more capacitance, which is harder to switch high and low at high data rates. But longer wires will still conduct current, and a continuity test is at low frequency, so something else is going on herre. Try measuring the actual resistance of the connecting wires instead ...


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