New answers tagged spi
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Yes, in particular, the clock signal of SPI is a problem at longer lengths. Think about it:
The master clocks data sent to the slave and those bits travel alongside each other down the cable so that is fine. But the master also clocks data sent by the slave which means that the slave can only send its bit when it receives the clock pulse. That the wires ...
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Wiring length can have a negative impact on SPI communication, which is best for communication between devices on the same PCB (short runs of copper). However, I do not think this is the cause of your problem. It sounds like you may have a defective strip, or defective cable, since you aren't getting continuity on your communication lines.
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Yes, the length of the wires used for SPI can affect the functionality. Longer wires give more capacitance, which is harder to switch high and low at high data rates. But longer wires will still conduct current, and a continuity test is at low frequency, so something else is going on herre.
Try measuring the actual resistance of the connecting wires instead ...
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I think I may have found the answer, after some more digging.
The RF chip seems to be PL1167.
Going through the register datasheet, I can see that register 0x23 is power management (first message that gets sent in my remote), 0x34 is FIFO pointer, 0x32 is FIFO data, 0x07 is TX enable, which coincides very well with what I'm seeing on the traces.
The ...
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There are 7+ mainstream STM32F0 MCUs with 8 USART interfaces. There are several high performance STM32F4/F7 chips with 4 USART + 6 UART (for 10 total) interfaces, and three dozen chips with 4 USART + 4 UART (for 8 total).
I am pretty sure you can find similar options from other manufacturers if you stop looking for DIP package. The adapters from LQFP to DIP ...
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The STM32F413 looks like it has 10 UARTS! https://www.st.com/en/microcontrollers-microprocessors/stm32f4-series.html
Even better for you, it looks like the STM32F413 is available on a Discovery Board, https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-discovery-kits/...
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Solved problem. There are bridge chips that can be controlled over I2C or SPI and have a UART.
Examples for the phrase "i2c uart ic":
SC16IS750/52/60/62
MAX3107
XR20M1172 (double UART)
Example breakout: http://www.aliexpress.com/item/32772833676.html
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You can also bit-bang a UART interface in software. This does not require dedicated UART hardware. Note however, that transmitting on a bit-banged interface takes more time than a hardware interface.
If you use Arduino, this might be of interest to you:
https://www.arduino.cc/en/Reference/SoftwareSerial
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RT_SPIM_CS_NONE - Don't do anything with the chip select.
You use this for erase bulk. But if you check datasheet p.114 figure 92, chip select must be asserted during bulk erase.
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So I tried some more stuff. Eventually I tried to read the REMS using an arduino that worked after sending a dummy byte while trying to retrieve data.
I now tried the same with the TI board and it returned data.
Updated function for retrieving the REMS is now:
//BLS_CODE_MDID = 0x90
uint8_t wbuf[] = { BLS_CODE_MDID, 0xFF, 0xFF, 0x00 };
...
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Flash memory is block device. This means that minimal erasable unit is block. Block consists of several pages. Page is a minimal writable unit. It is impossible that erase command clear only lower bits of each entry.
How you print data which is read from flash?
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If the part is not clocked, the data line will be tristated. It means, one can connect two datalines from two ADCs together to a single MISO pin of master (MISO pin of Arduino for example).
If you are using two ADCs to connect to Arduino, then have to use two GPIO pins extra to gate the SCL for the two parts.
In the below picture, you will get an ...
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What is being proposed is to gate the SPI clock with GPIO pins.
Looks like ATMega328 SPI controller stops the clock between transfers, so it’s practical to use clock gating. GPIO can be used to direct the clock to the appropriate device, with software changing the GPIO between transfers.
This ADC uses clock-idle low (CPOL=0), so the gating logic needs to ...
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A number of SPI slaves can be connected in one of two configurations:
Single Slave-Select daisy-chained
Here the entire SPI bus is treated as one big shift register and the master must know the order of devices in the bus chain and their respective register widths. It is also necessary to write all devices at the same time in the same bus transaction. ...
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i have changed crystal with 4 MHz.now mcp2515 is working fine.if i try to change its modes, it is changing to configure modes and normal mode only but not to any other modes.
very rarely, mode is changing to desired but not consistently. ** there is no issue with mode changing to configure modes and normal mode**.
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1m is not that much. Even in noisy environment good shielding and low speed should be enough to achieve reliable communication. That is, unless you are going to run this thing next to aircraft radar or ark welder.
A simple solution would be to use shielded CAT5/6 cable. One twisted pair would be SCK+GND, another MOSI+GND, and the remaining 4 can be used for ...
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I found it, flash size set incorrectly. I was sure that I set it right, so either cubemx or I made a mistake. After correcting it, problem solved.
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One meter, with a very good shielded cable may work. Since the slave select pins are basically DC lines, you can try it for sure. But you still have to care about the clock and the data lines. Opt for lower frequency as much as possible. I had interfaced 14 SPI lines from a mother board to all the daughter boards an about 50 cm of length. i had used MLVDS ...
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"What part of it sets the pin (MOSI) high and low to transfer bit."
This line:
SPDR = data;
sends the data out.
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Thank you fellas for your insights. Turns out, registering the SPI CLK is what got it done. I first had to bring back the FPGA clock as an input, then created a one-bit register 'sclk_r', then a new 'always' block which registered the wire input 'sclk' with the new register 'sclk_r'. The 'Pi SPI clock is about 1MHz. So, the FPGA is oversampling it at 50:1 ...
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You don't show the erase function, but depending on which size of erase you send, it may take more than 2000ms to complete. Full chip erase can take 10 seconds. You should check the flash status register if it says it's busy or not. Therefore it may not be ready for the first read command. And you don't enable write latch before byte write, so it will not ...
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I'm not sure if this is your problem, but I don't think you are handling the increment of count correctly. This variable can have exactly 8 values (in hardware) and you use all 8 of those values. So, there is no need to explicitly reset count when it reaches 111...just increment it and let it roll over to zero.
I am also suspicious of the logic that you use....
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Would it be necessary to use two separate SPI interfaces to try and
collect data simultaneously to calculate the current (Voltage across a
resistor), or would using a single SPI interface with two slaves be
sufficient?
If you want simultaneous sampling then you can cascade several ADCs so that you have a single SPI interface and a single start convert ...
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A first step to understanding this reading issue is to study the NAND Flash connections with an oscilloscope. Do this first without the BusPirate connected. With the circuit board in the same state as when you were trying to read see if the circuit board's other electronics is trying to make accesses to the NAND Flash. If there are other transactions then be ...
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Regarding PoE - It is not related to SPI vs MII choice. You can design your board to have a DC jack that bypasses the PoE regulator. Check the PoE reference designs from Aanalog Devices or TI for examples. Make sure your Ethernet connector and magnetics support PoE.
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