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37

Unless you have an initial state programmed, it will be more or less random. Although this may vary with different SRAM implementations. You also say "blank". Some might think that random is "blanker" than all 0's. SRAM memory stores memory on back to back inverters. This forms a bi-stable system (two very stable states with metastability dividing ...


33

The main driver is the fact that SRAM is highly compatible with the same physical process that is used to implement the actual logic. Indeed, most FPGAs these days are based on LUTs (lookup tables), which are really just tiny bits of RAM themselves. On the other hand, the process required to build EEPROM (nonvolatile memory) requires extra steps — to ...


23

FRAM is great, however, the technology has destructive reads. Flash technology has a limited write/erase cycles, but the reading cycles are almost unlimited. In FRAM, each read cycle actually affects the memory and it starts to degrade. TI states that they've found the FRAM has "Wear-out free endurance to 5.4 × 10^13 cycles and data retention equivalent of ...


21

In addition to Dave Tweed's answer regarding the fabrication processes involved, most flash-based FPGAs actually still use SRAM to drive their fabric. The bitstream is loaded into the SRAM from flash just like in a more conventional FPGA, the only difference is that the flash is internal. This architecture is evident when you look at their datasheets and ...


13

Your understanding is correct. An address is just an arbitrary label for a location. All locations are identical (from the PoV of the MCU), and as long as each MCU accessing the locations agree on what the labels mean (are wired the same) then it doesn't matter the slightest how you assign those "labels". As long as you use the same wiring for putting ...


11

From what I can see, the (main) difference between it and SRAM is it's slower, and the difference between it and EEPROM is it's more expensive. I'd say it's sort of "in between" both. Being a pretty new technology, I'd expect the price to drop a fair bit over the next year or so providing it becomes popular enough. Even though it's not as fast as SRAM, the ...


10

For the first question: There is 2kB of SRAM. There is an additional 32bytes of CPU registers, and a further 64bytes of I/O registers (things like the PORTA/DDRA/etc. registers). Add these all up we get 2048+32+64 = 2144bytes of addressable memory. Convert that to hexadecimal you get 0x860 - or in address terms 0x000 to 0x85F. The SRAM memory itself is ...


10

You are quite correct. With an SRAM, where all address pins are equivalent, you can indeed juggle the address pins around within their set on your board to ease layout, and also for the data pins. I would strongly advise putting a note on the board that you've done this, to avoid freaking out any subsequent engineer who comes along to debug or modify it. ...


9

The only real issue with FRAM is that for the really dense parts, the part of the market that drives volume and margin, they cannot yet compete on density (which is either a yield thing or a size thing - it doesn't really matter which). For the smaller parts (i.e. competing against older version of same technology) they do well. So yes, it's a good fit for ...


8

Let me point you to appnote AN4296 (for STM32F3). It talks about CCM in detail. It makes the distinction between Harvard and Von Neumann configurations. The CCM is intended exactly for executing code at maximum speed. That may be interrupt handlers, but also ordinary functions. There's a bus matrix. Both the CCM and ordinary SRAM have connections to data ...


8

For many kinds of chips, especially asynchronous static RAM chips, the arrangement of address, and the arrangement of data bits, are entirely arbitrary. Indeed, while manufacturers will generally number the address and data wires to match the pinouts of other devices, the sequence of wires within the chip may have no relation to their numbering. Some kinds ...


8

If we have a classical flip flop (like this image from wikipedia): You can see that depending on the state this is in, there is constantly some current flowing (and "stealing" current through the R3/R4 path, thus shutting that one off). The result then is never changing again, as long as VCC is active, thus the state of the whole apparatus is static. If you ...


8

I'll expand on my comment. A bit of background Pseudo SRAM is actually a dynamic RAM (DRAM) made to mimic a regular static RAM. Dynamic RAM allows packing much more bits in the same silicon area, so allows for bigger memory sizes (or cheaper price for the same size). The problem is, interfacing with DRAM is a bit more complicated, and, even more annoying, ...


8

More than anything, it depends on your requirements. While Size, Weight and Power (SWaP) are the main drivers for ICs in-general, if you aren't compelled to develop an ASIC because of those requirements, Performance is your next consideration, which may push you back to an ASIC anyway, but, you may be able to use an FPGA if you can afford the SWaP trade-...


7

This figure in the SRAM datasheet shows that the chip reads the data on the rising edge of the clock. That corresponds to two of your options, I guess the choice between the two is the edge on which the chip changes its output data. The figure below shows that it does so after the falling edge, hence your micrcontroller should read the bit 'on' the rising ...


7

16k x 9 means that the memory chip has a total of 16k locations in which it can store a binary number that consists of 9 bits. It will have a 14 bit address structure (14 bit gives you 16,384 locations in decimal). It may be a serial device but the address lines will still be there but internal to the device.


7

For sequential access flipping address bits around may cause a large increase in power consumption, if the flips will cause the SRAM to access new rows more frequently. If an SRAM module does not cover the entire addressable range (e.g. say the module has 768x128 bits), then a reordered address may cause you to accidentally address non-existing memory ...


7

Most 8, 16 and 32 bit microcontrollers execute the program directly from flash. This is true of the STM32F103 range. Most microcontrollers are capable of executing the program from RAM, but only relatively specialised programs actually do this. For this reason, most microcontrollers have far more flash than RAM. There are some microcontrollers that have ...


7

Is it possible to stack and static data collide? Yes, that is entirely possible. Atmega has no dedicated stack space, so if you use too much of it, you will overflow and crash your static data. Try to reduce your memory consumption (use the smallest suitable data types for variables, reduce your array sizes etc.) Make sure you don't have any recursion or ...


7

Some reasons : Pinouts are often standardized between static RAM and EPROM/FLASH: "JEDEC" RAMs are usually arranged in matrices with lines and columns. Using consecutive addresses may require a little bit less power. For events that affect the matrix, such as hardware defects or a SEU (high energy particle hitting atoms), knowing which memory cells are ...


6

First, don't confuse the interface (multiplexing the address lines) with the internal arrangement (laying things out in a matrix). All RAM chips use a matrix a the the lowest (single bit cell) level, most use a less regular layout at the higher level (for instance two separate banks). Multiplexing the address lines reduces the number of pins, but it has a ...


6

Yes, there may be physical damage. The longer the situation persists, the more the chance for damage. In case this is a problem you foresee happening often in your setup, you should probably work out a better scheme, or at the very least include a series resistor in each of the data lines. The resistor should be chosen such that in the worst case (both sides ...


6

256K x 8 means 256 kibi-locations, each location holding 8 bits. There are 18 address lines (218 = 256 * 1024) and 8 data lines.


6

What is the reason to add additional SRAM as CCM? The Cortex M3 and M4 Cores have 3 separate busses: Instruction, Data and "System". A transaction on one bus will not disturb other busses unless the same peripherial is accessed. You already mentioned DMA. The DMA controller can only access a RAM when there is no concurrent access from the M4 core - and ...


6

No fundamental reason why not. Synchronous SRAM is truly random access, fairly inexpensive, and easy to interface to. Its downside in that it occupies a fairly narrow niche between the on-chip BlockRam (not much smaller, free until it forces you to select a larger chip, massively parallel and more flexible) and external DRAM (massive storage capacity at a ...


6

Yes, the transistors in the SRAM cell are functioning as amplifiers; it is the internal positive feedback that creates the bistable operation that is used to store information. However, the sizes of these transistors are kept as small as possible so that more of them can be fit into a given amount of area, and to keep leakage currents as small as possible. ...


6

Try an STM32F4Discovery board; US$15-25. The MCU is an STM32F407VG: 168MHz ARM Cortex-M4, 1MB flash, 192kB RAM, 3 SPI ports and DMA that would, for example, allow you to stream from one SPI port to another with minimal processor involvement. The Discovery has a built in SWD programmer/debugger so no extra hardware is required; try CooCox for a free and ...


6

I think that the origin of the name comes from the convention for flip flops. On a D flipflop the data in pin is generally called D, and the data out pin, Q. Since the memories data bus is bidirectional, a data pin can be D when it is input or Q when it is output hence the name DQ.


5

Cycle as used on that web page means "clock cycle": the time taken for one pulse of the clock signal used by the ram. So the 100MHz clock corresponds to a 10ns cycle. Internally, this corresponds to selecting a row within the chip and reading the corresponding column lines; this brings out a set of values (let's say 256 bits = 8 bytes), for each of the 8 ...


5

What you're describing is called bus contention. I've personally only seen this cause damage once and I was using '80's era technology at the time. Most modern microcontrollers have bus arbitration logic built-in so that this won't happen when they are the only master. But if you have multiple bus masters, this can certainly occur. The most common symptoms ...


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