You are correct in a way, in the cortex m (which your stm32 is, though I can't say which variant unless you specify a part) there is one active stack pointer r13, this can however be either the MSP or PSP. The reason for two is to enable the user to easily implement a multi tasking 'operating system'. The idea is that the PSP or process stack pointer is ...


These instruction sequences are not equivalent, they are 4 different ways of implementing stacks. A is a top-down stack where the stack pointer addresses the most recent value. B is a top-down stack where the stack pointer addresses the next insertion point C is a bottom-up stack where the stack pointer addresses the most recent value D is a bottom-up stack ...


The msp430 is natively 16 bit. It has a 16 bit, 2 byte bus. Memory addresses are still numbered in 8 bit, 1 byte increments, as this is the standard for memory addressing. This is why the stack is evenly aligned.


Each memory address references a single byte, but the internal data bus (and flash memory) of the processor is 16 bits wide. When accessing values in memory that will be used for data, this is irrelevant from a hardware perspective; it's something the compiler will deal with. When accessing values in memory that will be executed, i.e. are machine code ...


As per my understanding, each address location in RAM can store 16bits of data No, each RAM address stores 8 Bits of data, or one Byte.


You would normally set the stack pointer at the start of your program. I think the usual initial value for the stack pointer would be the top of available RAM (but its a long time since I used an 8085/Z80 style microprocessor).


TL;DR? skip to the short answer at the bottom. This appears to be a cortex-m based microcontroller. Which means you need the datasheet and other reference materials from Atmel/Microchip. In that documentation it will state cortex-mX -m3 -m4 -m7 -m0 -m0+ one of those, so you go to arms website and get the technical reference manual for that core. In that ...


I was under the impression the Cortex M4 automatically loaded the first and second entry in the vector table into the SP and PC registers. Is this not the case? It should. 0x0 contains stack pointer. 0x4 contains reset handler address. LR should also have been cleared to FF. I suspect your debugger is not resetting the core correctly.


The return address saved on the stack must be of instruction after the HALT instruction Of course. Otherwise the CPU would go into a HALT instruction again after returning from the interrupt. Suppose this processor has 32 bits Load/Store operations, ALU operations is 16 bits and Branch instruction is 16 bits. Some information is missing: Either the ...

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