Episode #125 of the Stack Overflow podcast is here. We talk Tilde Club and mechanical keyboards. Listen now
15

To answer your questions: Using thin prepregs is not uncommon, and in your case for example the standard 1080 prepreg is close to your 3mils thickness. ( a list of the most common thicknesses can be found here) The issue I see is that you are using a buildup construction, which non all manufacturers are comfortable with using. Another thing that is worth ...


13

The theory says that the current return path at high frequency is on the reference plane right under(or above) the signal trace. I know it is true and I have always assumed it was, but I would like to understand it properly. There are far too many ambiguous words describing your scenarios so draw a picture but, in the meantime consider what happens when ...


9

The problem is indeed with the crossing 1-15 and 2-16 vias. The manufacturer has to be physically able to make the board. There may be a way to attempt that construction, depending on the equipment the manufacturer has. There are two straightforward ways to get close to what you have drawn. 1) 1-2 core, drill, thru plate. 15-16 core, drill, thru plate. ...


8

Difference between core and prepreg is that core has cooper filled on both sides of dielectric and prepreg is just full dielectric, no copper on any side of the material. Since you just sandwiched the prepreg between two cores, which are themselves clad with copper, the prepreg now has copper on both sides of it. Why wouldn't return current flow on the ...


5

As far as I'm concerned, Stackup 2 is a no-go, because it's non-symmetric. The upper thick dielectric layer is 3rd from the top, but the bottom thick dielectric layer is 2nd from the bottom. This can cause warping of the finished boards, which will lead to further problems. So if these are your only two choices, you should choose stackup 1. Because I ...


5

As long as GND and VCC are connected by several capacitors at both sending and receiving end of signal lines (as they should be, will be in high speed design), AND where the return current changes planes (which you should try to avoid) then it doesn't matter which plane the return current flows in. The return current is only interested in the AC impedance of ...


5

Theoretically it does not matter as long as you provide proper coupling between different reference planes. The following animations illustrates the current flow in transmission line, Wikipedia gif. Moving dots illustrate local charges. As one can see, the charges oscillate along conductors, including the reference plane. When you switch planes, you need to ...


4

In this design, the return current of high speed digital signals in layer 4 will be almost equally distributed between layers 3 and 5. This is OK until layer 3 has no discontinuities (isolation gaps) along any of digital lines. Careful routing may help to achieve this goal. Then your planes 1 and 2 stay "clean" of digital signals. If you can not avoid gaps ...


4

Without agreeing that you should do this, it's possible to make all the connections you want using mechanically drilled blind vias. You might find you need to make the diameter of the deeper drills (like layer 1 to layer 15) fairly large to ensure good plating in the via. One vendor I just checked requires an aspect ratio less than 1.0, so you'd have a ...


3

This is actually not that bad of a layout because the middle prpeg layer is normally the thickest. Because capacitance between two conductors is determined by the area and the distance between the conductors, the middle layer maximizes the distance. In fact it increases the distance by a factor of 4-8 which means 4 to 8 times less capacitance between layers ...


3

It depends on what the signals are. In a 6-layer PCB, you've probably got quite a lot of parallel buses to get from place to place. So common technique is to route each of the two adjacent signal layers with tracks perpendicularly as much as possible; one of the layers predominantly 'north-south', and the other layer predominantly 'east-west', avoiding ...


3

So, what am I missing? From this point of view, the thick-prepreg stackups of some manufacturers are useless. But they exist (and in fact are standard!) for some reason. How do people use them? I think what you're missing is the fact that majority of four-layer boards will not have ANY controlled impedance lines. Therefore, any old prepreg thickness ...


3

Well hopefully you don't have 1" spacing between your layers because that's a heck of a thick board :) You can use layer 3 for small local power planes and routing but the consequences I can think of would be the following: Traces on layer 4 will reference the reference plane on layer 2 if there is no reference plane below them on layer 3. As you say the ...


3

The increased spacing in the middle lowers the effectiveness of plane capacitance which depending on your application may or may not be useful to you. The decreased spacing from signal to plane will let you use thinner traces to achieve similar impedances, while reducing the effect of cross talk between signals (assuming the same trace to trace spacing in ...


3

A power plane is just as good a reference plane as a ground plane, and will serve as the reference plane/return path for its adjacent signal layer as its just as good an AC ground as the ground plane is -- so there's no reason to do the routing convolutions you describe.


2

"High speed" return currents will follow the path of least impedance. "Low speed" return currents will follow the path of least resistance. This means that high speed signals tend to return on the return path that is closest to the signal path. In other words, if you had an S shaped signal above a ground plane, the return current for a high speed signal ...


2

The main consideration is that any high speed or sensitive analog tracks should run over an unbroken reference plane. This could be a power plane or a ground plane, but these sensitive tracks shouldn't run over a split in the plane. Without knowing more about your design I can't say whether you have enough ground planes or if you need to figure out how to ...


2

trying to figure out how I can replace a 4" trace with an equivalent RLC Circuit. First choice: Don't. Use the 'tline' element in LTSpice instead. Second choice: You can model a transmission line with a sequence of pi or T sections. If you use a different transmission line calculator, for example the Saturn PCB one, or this online one, they will output ...


2

Having spoken to PCB manufacturers here in the US and one in Europe specifically about this issue, I learned the following: PCB manufacturers control the final thickness of the finished boards as well as the dielectric layers formed using prepreg compression and resin flow. The finished thickness is important for differential pair and other controlled ...


2

What are the advantages and disadvantages of one versus two plies? For controlled impedance, you get the best performance with zero plies. That is, if you are concerned about a repeatable RF performance between certain layers in a multilayer PCB layup, you should arrange for the impedance critical layers to be separated by core. If pre-preg between signal ...


2

For boards with lots of high frequency routing requirements the problem is solved by using more layers and assign more of them to be ground planes. For example a 6 layer board may use a stackup like this: surface routing layer reference ground layer for 1 & 3 inner routing layer power plane (may be segmented if more than one voltage rail) reference ...


2

As others have mentioned, symmetry is very important with PCB stackup, so you should really aim for that. FR4 can withstand 20 kV/mm (according to Wikipedia, you probably want to verify this from the fab). You require 7.4 kV, so it should be more than enough if you make the thickness of 1-2 and 15-16 both 0.8 mm, which would result as a symmetric stackup. ...


2

I would like to suggest that your proposal to use these blind and buried vias makes for a much more expensive board. You really should look at using more than 4 layers to be able to achieve your layout whether that be 6 or 8 layers. In all likelihood the cost for such board will be cheaper than your 4 layer board with the fancy expensive vias. More layers ...


1

AFAIK the "stackup" will be called a "layup" at the PWB shop. your problem for the calculation you're making is it doesn't have tolerances. you need to find the worst case because it will be the first production lot. everything is variable including Er as the glass/epoxy ratio varies. You need to nail down the corner cases. You also have a lot of ...


1

You have some things to consider in the layout process. It is common to use the required narrow trace (you indicated 5 mil) to breakout from the BGA pin field. As soon as you clear the pin field you expand the trace width to achieve the desired impedance for the route over to the DDR3 chip. Of course that routing depends upon your stack-up and calculated ...


1

The said chip is an adaptive filter chip which accepts either differential pair or 50Ω signal. Get rid of the unnecessary impedance matching pad to convert 75 to 50 ohm: - The front page of the data sheet says this: - Equalizes up to 120 Meters of Belden 1694A And Belden 1694A cable is already 75 ohm. Belden 1694A is an excellent, low loss 75 ohm ...


1

I don't know of any advantage or disadvantage of using multiple vs. single plies. However, be aware that different glass weaves have different Dk and Df values. You should also be aware that tighter weaves will result in thicker pressed thicknesses compared to looser weaves - resin doesn't flow as easily between tight strands vs. loose strands. This can also ...


1

For controlled impedance and low noise you'd like the signal traces to run over a continuous ground plane. In theory the power plane might act in a similar manner, however with many boards it is desirable to split the power plane into different regions, whereas the ground plane is usually left intact (at least up to isolation barriers). You do not want to ...


1

There is a lot a parameters to take into account when you make a PCB and with DIY PCB fab, some information may be missing. For instance MacroFab's stackup state a 1.6 mm PCB thickness, but is this the final thickness, after lamination or before ? Also what's the margin on this thickness. Also impedance have often a 10% margin to take into account ...


1

The test specifications for at least one connector (items 3.1.5 and 3.1.6) suggest that the range of allowable thickness would be 1.44 to 1.70 mm (0.057 to 0.069 inches), which would be a tolerance of about ±8%.


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