40 votes
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VHDL interview question - detecting if a number can be divided by 5 without remainder

Doing a remainder operation in serial fashion is actually quite easy. The key assumption is that the data comes in MSB-first if it's serial. You only need N states to compute a remainder modulo N. ...
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17 votes

Interrupt handling in microcontrollers and FSM example

The first tactic is to architect the overall firmware so that it's OK for interrupts to occur at any time. Having to turn off interrupts so that the foreground code can execute a atomic sequence ...
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16 votes

VHDL interview question - detecting if a number can be divided by 5 without remainder

You can also design a state machine if the data comes LSB-first: The existence of such a deterministic finite automaton (DFA) directly follows from the other answer, which describes the DFA for MSB-...
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  • 261
14 votes
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Finite State Machine FSM

Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address ...
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  • 21.6k
8 votes

Embedded programming state machines

I'd be surprised if there's a big difference on a 32-bit MCU. Avoiding conditional branches could save you a few cycles, but are you really going to succeed or fail based on a few cycles? The number ...
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  • 20.7k
8 votes

What's importance of finite state machines (FSM) with respect to embedded systems implementation?

A FSM is a structured method of constructing a sequential machine. The machine can only exist in a fixed number of discrete states - ie ‘finite state’. FSMs can be formally proven for correctness. ...
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  • 5,422
7 votes

Interrupt handling in microcontrollers and FSM example

If you need a critical section, you must make sure, that the operation guarding your critical section is atomic and cannot be interrupted. Thus disabling the interrupts, which is most commonly ...
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7 votes

VHDL interview question - detecting if a number can be divided by 5 without remainder

One way to come up with the (MSB first) state machine is as follows: The number received so far is N. Assume you know the remainder ...
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  • 5,008
7 votes
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Is a combinational logic circuit a Finite State Machine?

EDIT: This answer is answering the original question, that was edited later: "Is combinatorial logic can be seen as a subset of FSM". Combinatorial circuit is a Finite State Machine. In ...
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  • 9,751
6 votes
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State based vs State-less design (in verilog)

Even though a design may be considered 'stateless' because there is no explicit state machine, you may still be actually coding a type of state mechanism without explicitly calling it that. For ...
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  • 5,334
6 votes

Finite State Machine FSM

This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are ...
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  • 822
6 votes

State Machine with D Flip Flops; how to deal with race conditions

Edge-triggered FFs generally will not "beat" their own input setup and hold time requirements. You can usually string them directly together to form shift registers of arbitrary lengths. Therefore, ...
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6 votes

how to implement several large state machines in hardware?

implementing a bigger state machine would possibly reduce fmax of a design anyway. That would imply a state machine where the "next state" decision is overly complex. That's a criterion for ...
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6 votes

Does this combinational lock circuit contain any memory?

Does this circuit have any memory or state? If you ignore glitches or other transient phenomenon then no, it has no memory or state. The output is a fixed function of the input only, not on prior ...
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5 votes

Interrupt handling in microcontrollers and FSM example

If you've determined that a section of code must run uninterrupted then, except under unusual circumstances, you should disable interrupts for the minimum duration possible to complete the task, and ...
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5 votes
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Why is this a Moore and not a Mealy FSM?

As written there, "Moore outputs are synchronous with the clock, only changing with state transitions. Mealy outputs are asynchronous and can change in response to any changes in the inputs, ...
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  • 666
5 votes

VHDL interview question - detecting if a number can be divided by 5 without remainder

One hopes the interview question was about how you would solve the problem, rather than the ins and outs of VHDL or Verilog. The language details are straightforward once you have an algorithm. If ...
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5 votes
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Moore vs mealy, why the output is delayed in the former?

Moore outputs are synchronous with clock. It changes only with state transition at clock edge. Mealy outputs are asynchronous. They can change immediately with input change, independent of the clock. ...
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  • 2,709
5 votes
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Digital Logic: What are "hamming code" and "Binary code" state machines?

If you have a state machine with N states, there are a number of different ways to encode those states as binary logic. One-hot encoding assigns one FF to each state, so it requires N FFs. Only one ...
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5 votes

How can I convert a 4-digit BCD number to Binary in hardware? (using 74LS ICs and GAL22V10 ICs)

Since you appear to be happy to user older technology, you could use a 16-bit xPROM (Flash EPROM or EEPROM if you prefer). Feed the BCD into the address lines and take the result from the bottom 10 ...
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  • 776
5 votes

Does this combinational lock circuit contain any memory?

If, and only if, the eventual stable output of a system depends only on the current input, that system is by definition memoryless.
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4 votes
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Pressing same key rows at the same time

The short answer: Invert your logic. Drive the column select lines with open-drain (or open-collector) logic where the selected column is pulled low and the un-selected columns are floating. When you ...
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  • 4,135
4 votes

You need at least four states to exploit the advantages of a Mealy machine over a Moore machine

With a Moore state machine, the number of possible output combinations (I hesitate to say "output states") is no more than the number of internal states. With a Mealy machine, the number of possible ...
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4 votes
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This state machine does not go into an initial state on start

This is exactly why a Reset signal is added to the system. To bring it to an initial known state. There is no way to avoid it when working with actual hardware. As ...
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  • 9,751
4 votes
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When to use State Machines - FPGA

If you have to split an operation across multiple clock cycles, you have two options : pipelining, and sequencing Let's consider a mythical operation consisting of four multiplications , for example -...
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4 votes
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ASM chart to circuit

Yes, the one hot method. For a state diagram of N states, use N d-type flipflops and a code that has N - 1 zeroes and a single 1. When you are in S0 then the S0 flipflop has a '1' in it. It is hot. ...
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4 votes
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Is there an example of a Mealy state machine that can not be converted to a Moore?

Yes. A Mealy model can produce an asynchronous output for an asynchronous input whereas a Moore output is always synchronous. This can be useful when the output is required earlier than the next state ...
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  • 470
4 votes
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Is there a "standard" way to verify HDL of a state machine?

Verification is a huge part of the design process; in a complex design, it would not be unusual to spend as much time, or even more time on verification than you do on the actual design. That being ...
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  • 1,957
4 votes

Where finite-state machine code belong in µC?

I am working in automotive industry. You often see such endless loops in situations where the CPU should reset - just like this: ...
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