# Tag Info

Accepted

### VHDL interview question - detecting if a number can be divided by 5 without remainder

Doing a remainder operation in serial fashion is actually quite easy. The key assumption is that the data comes in MSB-first if it's serial. You only need N states to compute a remainder modulo N. ...
• 176k

### VHDL interview question - detecting if a number can be divided by 5 without remainder

You can also design a state machine if the data comes LSB-first: The existence of such a deterministic finite automaton (DFA) directly follows from the other answer, which describes the DFA for MSB-...
• 261
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### Is a combinational logic circuit a Finite State Machine?

EDIT: This answer is answering the original question, that was edited later: "Is combinatorial logic can be seen as a subset of FSM". Combinatorial circuit is a Finite State Machine. In ...
• 10.1k
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### Moore vs mealy, why the output is delayed in the former?

Moore outputs are synchronous with clock. It changes only with state transition at clock edge. Mealy outputs are asynchronous. They can change immediately with input change, independent of the clock. ...
• 2,772

### What's importance of finite state machines (FSM) with respect to embedded systems implementation?

A FSM is a structured method of constructing a sequential machine. The machine can only exist in a fixed number of discrete states - ie ‘finite state’. FSMs can be formally proven for correctness. ...
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### VHDL interview question - detecting if a number can be divided by 5 without remainder

One way to come up with the (MSB first) state machine is as follows: The number received so far is N. Assume you know the remainder ...
• 8,913
Accepted

### Is there a "standard" way to verify HDL of a state machine?

Verification is a huge part of the design process; in a complex design, it would not be unusual to spend as much time, or even more time on verification than you do on the actual design. That being ...
• 2,027

### Finite State Machine FSM

This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are ...
• 840

### State Machine with D Flip Flops; how to deal with race conditions

Edge-triggered FFs generally will not "beat" their own input setup and hold time requirements. You can usually string them directly together to form shift registers of arbitrary lengths. Therefore, ...
• 176k

### how to implement several large state machines in hardware?

implementing a bigger state machine would possibly reduce fmax of a design anyway. That would imply a state machine where the "next state" decision is overly complex. That's a criterion for ...
• 97.5k

### Does this combinational lock circuit contain any memory?

Does this circuit have any memory or state? If you ignore glitches or other transient phenomenon then no, it has no memory or state. The output is a fixed function of the input only, not on prior ...
• 46.7k
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### Why I am getting one clock cycle delay in Verilog case statement?

At the positive edge of clk you change from WAIT state to SERVE state. You don't change the ...

### VHDL interview question - detecting if a number can be divided by 5 without remainder

One hopes the interview question was about how you would solve the problem, rather than the ins and outs of VHDL or Verilog. The language details are straightforward once you have an algorithm. If ...
• 837
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### Digital Logic: What are "hamming code" and "Binary code" state machines?

If you have a state machine with N states, there are a number of different ways to encode those states as binary logic. One-hot encoding assigns one FF to each state, so it requires N FFs. Only one ...
• 176k

### How can I convert a 4-digit BCD number to Binary in hardware? (using 74LS ICs and GAL22V10 ICs)

Since you appear to be happy to user older technology, you could use a 16-bit xPROM (Flash EPROM or EEPROM if you prefer). Feed the BCD into the address lines and take the result from the bottom 10 ...
• 961
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### Design of non-overlapping "1010" sequence detector

After detecting "1011", why does the detector go back to B The diagram is correct for the non-overlapping sequence. To get into state D requires the sequence 101. If the next input is 1 (...
• 8,686
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### ASM chart to circuit

Yes, the one hot method. For a state diagram of N states, use N d-type flipflops and a code that has N - 1 zeroes and a single 1. When you are in S0 then the S0 flipflop has a '1' in it. It is hot. ...
• 106
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### Is there an example of a Mealy state machine that can not be converted to a Moore?

Yes. A Mealy model can produce an asynchronous output for an asynchronous input whereas a Moore output is always synchronous. This can be useful when the output is required earlier than the next state ...
• 470

### Where finite-state machine code belong in µC?

I am working in automotive industry. You often see such endless loops in situations where the CPU should reset - just like this: ...
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### How do I eliminate latches in FSM Verilog implementation?

What I see is the coding style where you have a registered and a combinatorial section. It is a good coding style but it also only works if you are 100% consistent in your code: Everything you clock (...
• 14.5k
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### How would I finish out this mini project (emitting 1 whenever 101 is read)?

Confession I'm not classroom-trained on Mealy and Moore. I'm only "book-read" and, prior to that reading, only had lots and lots of basic practice from making things work using state machines (...
• 78.4k
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### Attach output to a state in Finite State Machine in VHDL

For writing concurrent code (outside of a clocked process), try this: ...
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### What kind of FSM is it, if outputs depend on internally generated signals?

The counter value is actually part of the state of the machine. Everything that is stored in a flip-flop inside the machine and has the potential to change the behavior of the machine is its state.
• 31.6k
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### '1011' Overlapping (Mealy) Sequence Detector in Verilog

The error is caused by mixing the combinational State assignment block with the sequential output block. The combinational state assignment block and the sequential output block have different ...
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### '1011' Overlapping (Moore) Sequence Detector in Verilog

Your state variable is too small. You have 5 states, but your variable is only 2 bits wide. It must be at least 3 bits wide. Change: reg [1:0] PS,NS ; to: ...
• 8,686
Accepted

### How can I convert a 4-digit BCD number to Binary in hardware? (using 74LS ICs and GAL22V10 ICs)

I dont know how I would subtract the 3 from the input digits without changing the number first into 2's complement and then back to binary and feed it into the register. This isn't as complicated as ...
• 176k

### Does this combinational lock circuit contain any memory?

If, and only if, the eventual stable output of a system depends only on the current input, that system is by definition memoryless.
• 22.9k
Accepted

### Error: Iteration limit reached within 195 ns

That error commonly occurs when you have a combinational loop in your code. For example, look at the costp signal in this code: ...
• 8,686