Skip to main content
23 votes
Accepted

Why do non-synthesizable commands even exist in VHDL?

Those parts of VHDL exist for use in testbenches. Being able to simulate a VHDL design under a VHDL testbench is an essential step in the VHDL development process. Verification is proving a design ...
TonyM's user avatar
  • 23.5k
18 votes
Accepted

FPGA register initialization

the FPGA synthesizer ignores these code parts completely? Both Quartus (Altera/Intel) and Vivado/ISE (Xilinx) respect initial statements for synthesis (as do some others). You can use them to set ...
Tom Carpenter's user avatar
13 votes
Accepted

Detect the first rising edge of 3 input signals

You could use the circuit below with 3 D flip-flops and one 3-input AND gate. You would also need to use the reset input of the flip-flops to bring the output back to zero (not indicated in the ...
joribama's user avatar
  • 2,237
11 votes

Why is synthesis so slow compared to compilation?

Compiling a kernel is a process which simply takes some source code and then linearly converts and links it as machine code. Synthesis is a process which involves making multiple iterations of the ...
RoyC's user avatar
  • 10.1k
8 votes
Accepted

Handling inferred clocks during RTL Synthesis

You have added an FPGA tag, so I will answer from an FPGA perspective. If you are creating an ASIC or using some other flow, a different answer might apply. 1. Why ...
scary_jeff's user avatar
  • 2,017
8 votes
Accepted

Partially associated formal cannot have actual OPEN in VHDL under Vivado

In VHDL, you cannot connect an individual element of a port to open. You must connect either the whole port to open, or connect ...
scary_jeff's user avatar
  • 2,017
8 votes

Synthesis of Analog Circuits With a Desired Input and Output Characteristic

As pointed out @Tim Williams, this can be done simply, something like this. Just adjust some components ... But as you are using some DSP, this can be done also with simple software.
Antonio51's user avatar
  • 14.4k
8 votes
Accepted

Why can't you mix edge signals with level signals in SystemVerilog for synthesis?

Your example, and the standard negedge rstN do not have the same behaviour. Let's see why. I assume we are trying to make a positive edge clocked D-FF with an ...
Tom Carpenter's user avatar
7 votes
Accepted

Why isn't this decoder being inferred as a LUT?

The RTL schematic shows you how it has interpreted your code. As you can see, it has the exact combination of AND gates and multiplexers that your code describes. ...
scary_jeff's user avatar
  • 2,017
7 votes
Accepted

Synthesis of Analog Circuits With a Desired Input and Output Characteristic

To be clear, Fourier transforms do not apply to a DC transfer function, at least not profitably, in any context I can think of offhand. But we can apply other kernels to approximate or solve for a ...
Tim Williams's user avatar
  • 39.5k
6 votes

Detect the first rising edge of 3 input signals

Put each input on the set of an SR latch, and AND all the outputs together.
Scott Seidman's user avatar
6 votes

Synthesis rules for this procedural assignment (combinational circuit)

a = -a ; a = a << 1 ; Both these statements inside the combinatorial always block are not valid for synthesis at ...
Mitu Raj's user avatar
  • 11k
6 votes

Can a digital designer beat synthesis tools?

For logic crunching of combinatorial HDL into combinatorial gates i.e. LUTs, then the synthesis tool will produce exactly the same firmware. I've actually done the exercise you're describing and much ...
TonyM's user avatar
  • 23.5k
6 votes
Accepted

Can a digital designer beat synthesis tools?

Can a digital designer beat synthesis tools? The synthesizer will likely always find an optimal solution for any reasonably simple Boolean function. To be useful, HDL needs to run on some sort of ...
user4574's user avatar
  • 12.4k
6 votes
Accepted

Will FPGA synthesis tools ignore unused modules?

Unlike software where the compiler will sometimes keep code around that isn't actually called (particularly for things like libraries), this isn't the case for HDL designs. This is because HDL isn't &...
alex.forencich's user avatar
6 votes
Accepted

Are the initial conditions for reg and wires synthetizable in Verilog?

Yes, initial values for reg are supported in Artix (and the majority of other) FPGAs. Opinions differ on whether it's a good idea to rely on it; there are some ...
TypeIA's user avatar
  • 2,426
6 votes
Accepted

How do FPGAs implement the inequality operator?

Let's just derive the circuit ourselves. The key is to break the operation on the input integers down into smaller pieces. Given two numbers, for example 234 and <...
Jonathan S.'s user avatar
5 votes
Accepted

How is ASIC design different from FPGA design? Do you write HDL (Verilog, VHDL) to design and ASIC the same way you would for an FPGA?

1) not all ASICs are digital-only. Some have analog circuits as well or are even analog-only. So your question only applies to digital-only ASICs or only the digital part of an mixed-signal ASIC. ...
Bimpelrekkie's user avatar
5 votes
Accepted

VHDL optimization

My guess is that there will be no difference. However, the results will depend greatly on the specific tool set you use as well as the target architecture (FPGA? ASIC?). By the time the tools get to ...
Elliot Alderson's user avatar
5 votes
Accepted

Parametric bit-width assignment in Verilog

You were very close. The proper syntax is as follows: CODE <= {BUS_WIDTH{1'b0}}; CODEreg <= {BUS_WIDTH{1'b0}}; Refer to IEEE ...
toolic's user avatar
  • 8,561
5 votes
Accepted

Non-constant index in a synthesizable Verilog deserializer

While it is not possible to use a variable index inside the standard [:] parts select, because you could declare different widths, there is the indexed part select ...
Tom Carpenter's user avatar
4 votes
Accepted

Introduce delay on a single bit signal w.r.t. input clock

That is not a correct way to add a delay. This technique will lead to missed pulses, or wrong pulse length. Bascially, here, you're just synchronizing your output every 4 cycles. To make a proper ...
dim's user avatar
  • 16.1k
4 votes
Accepted

Is there any tool that can create a logic circuit equivalent to some Verilog code?

Just about any FPGA/PLD tool should be able to do that. In the somewhat obsolete Xilinx ISE Project Navigator that I currently have open the first item under Synthesize is "View RTL schematic". ...
Andrew's user avatar
  • 6,912
4 votes
Accepted

Assigning the different value to parameters in Generate block in Verilog

You can do this easily in SystemVerilog as you can declare a parameter that is an array and then select index of the parameter array inside the generate loop. Most simulation and synthesis tools ...
dave_59's user avatar
  • 8,630
4 votes
Accepted

VHDL Flip Flop Syntax Error

You have a few issues: 1. endif; should be end if; 2. You already have assignments to ...
Blair Fonville's user avatar
4 votes
Accepted

What is the purpose of this Verilog code for implementing 3-port Block RAM?

This has been unanswered for a day and I think I know why. If Verilog code becomes a bit bigger and complex it is very difficult to see all the temporal relations. Even if the user puts lots of ...
Oldfart's user avatar
  • 14.5k

Only top scored, non community-wiki answers of a minimum length are eligible