30

I assume you are not alluding to a deeper philosophical discussion about information, power and entropy, but you are just interested in the practical aspects. Very simply put, digital circuits need to measure input, digitize it, run it through some kind of processing and then transform the output into an electrical signal again. Digital circuits cannot ...


14

At a place I worked there were two camps of FPGA designers. One camp I called simulate, simulate, simulate or s cubed. The other camp was all about design. The s cubed guys used a simulator like modelsim, they would come up with an initial design via coding methods and\or blocks in the design suite. Then they would simulate it and find the things that ...


13

You could use the circuit below with 3 D flip-flops and one 3-input AND gate. You would also need to use the reset input of the flip-flops to bring the output back to zero (not indicated in the schematic). simulate this circuit – Schematic created using CircuitLab


11

Yosys does exactly what you want and supports a large portion of Verilog-2005. Have a look at the */rtl/ directories at https://github.com/cliffordwolf/yosys-bigsim/ for examples that can be synthesized with Yosys. Disclosure: I am the author of Yosys.


10

I will leave it to an LRM expert to provide a more detailed answer, but in short, your approach should be valid - I ran a quick test with a recent version of Quartus, and it handles '-' like it's supposed to - the logic generated is reduced as expected when the output is defaulted to '-' ('X' works too, by the way). More on the approaches you listed: Not ...


8

I would distinguish three possibilities: A VHDL variable has no hardware representation at all. Assume the following example signal a,b,c : integer; ... process ( clk ) is variable var : integer := 0; begin if ( rising_edge(clk) ) then var := a + b; c <= var; end if; end process; The variable var is not really synthesized as ...


7

In addition to SomeHardwareGuy's excellent answer, try to break the job into smaller tasks that you think you can understand, then design each of those (breaking them into smaller tasks if necessary). For your door lock, some tasks may be: read the keypad compare entered number to combination start with hard-coded combination, when working, think about ...


7

Here is a D flip-flop spec'ed to operate at 40 Gbps. Setup and hold times are advertised as 4 ps. It consumes only about 750 mW. These are manufactured with a SiGe process, although I don't know which one. There are several foundries offering SiGe process, including GlobalFoundries, TSMC, and TowerJazz.


7

The RTL schematic shows you how it has interpreted your code. As you can see, it has the exact combination of AND gates and multiplexers that your code describes. If you want to know how it has mapped this into the FPGA resources, you need to look at the 'technology schematic'. Note that the technology schematic is hard to navigate unless you set the ...


7

You have added an FPGA tag, so I will answer from an FPGA perspective. If you are creating an ASIC or using some other flow, a different answer might apply. 1. Why is there an inferred clock on pstate[1] in this design? offset_val <= ctr1 when pstate = s2; This line does not describe anything happening when pstate is not s2. This constitutes a gated ...


7

In VHDL, you cannot connect an individual element of a port to open. You must connect either the whole port to open, or connect some elements to your intended signals, and others to 'dummy' unused signals. So you have a couple of options: Q8 => open, -- Just associate the whole port with `open` if for some reason you must use individual association: ...


6

There's nothing wrong about using integers for RTL per se, but there are reasons that some avoid it. This really is a question about subjective "best practice" and you'll eventually have to find out yourself what you prefer. As a help to that, I'll share my experience and thoughts on this. Principally , I'm in favour of using (constrained) integers, also ...


6

There are some open research synthesizers that are getting close - VTR (Verilog to Routing) and Yosys Open SYnthesis Suite deliver the most promising tools. If your aim is to deliver a chip rather than research routing algorithms then (at least in 2013) you need vendor tools.


6

Digital processes inherently add a certain amount of latency since an event that happens between two clock cycles can't be processed until the next one and, to avoid problems with events that happen very close to clock-cycle boundaries, things are often designed so that events won't take effect until the second clock cycle after them (trying to decide ...


6

In short: It's legal VHDL and it's typically supported by synthesis tools. It is however rather uncommon to see it used. I don't really know why. Your code seems to me to be a good example of when it would be meaningful to use it. There is however one drawback that one should be aware of: at synthesis, the functions driving outputs where don't care's are ...


6

Main things are: Careful coding to avoid non-synthesizable structures Minimize logic levels for better timing performance (make logic between registers as simple as possible) test, test, test to ensure functional correctness and check for things like uninitialized regs and disconnected wires synthesis and check synthesis logs for warnings, make sure the ...


6

Put each input on the set of an SR latch, and AND all the outputs together.


5

If you use the value in a variable before you store it, you get the value that was stored last time the process stored it (in a clocked process, the value from a previous clock cycle). That is synthesised as a register or FF. Of course, in the first clock cycle you get garbage, unless you initialised the variable in a reset clause.


5

I am sure that they can be implemented with linear elements: resistors, inductors and capacitors. I wouldn't be so sure about that. A trivial counter-example is \$H(s) = K, K > 1\$. A less trivial counter-example is any \$H(s)\$ with RHP poles or any with a finite impulse response. RLC circuits cannot implement an arbitrary transfer function. ...


5

Synthesis is highly dependent on the platform you're using and usually needs to be done by tools created by Altera, Xilinx, etc. Nothing open source exists (AFAIK) because this is so custom and requires a lot of effort to obtain optimal and correct results. Therefore, there's little incentive to do open source. Also, because of the IP, these companies don't ...


5

Think: Well first you think about what you want to do, why you want to do it and for who are you doing it for. Is it just for yourself to learn? Or are you hoping to take the combination lock market by storm with your new iphone controlled padlock? Research: Then you do a little research. What kind of electronic combination locks are out there today? ...


5

No it's no error. Synthesis just estimates timings because you didn't apply any constraint file. In the normal ISE flow, constraints are applied in the translate step. If this is to late and you need earlier constraint checks or optimizations, then you can apply a XST constraint file (*.xcf) with timing information. The syntax is the same as in ucf files ...


5

Synthesis tools work very hard to evaluate everything at compile time that they possibly can. For everything else, they synthesize logic -- including function calls, assuming that the function is synthesizable (some are not). Therefore, the answer to your question is, "it depends". It doesn't matter if the actual parameter to the function is a generic or a ...


5

VHDL-2008 has synthesisable fixed-point and floating-point libraries, in addition to ieee.math_real which is strictly for simulation. You can instantiate the float package with any width of mantissa and exponent, or use the pre-defined float types (roughly IEEE P754). The fixed point package is a better choice for DSP, and usually produces smaller hardware. ...


5

All your synthesizable code needs to be expressable as: LUTs Flip-flops Vendor-specific primitives Vendor-specific primitives are either instantiated explicitly, or generated by the vendor's wizard, or inferred by very specific coding patterns, so there shouldn't be any ambiguity there. In VHDL for example, you can't use wait for in synthesizable code. ...


5

If you know precisely what you want to end up with, there's no need to have Xst try to infer it from a behavioral model. You can instantiate a block RAM object directly in HDL code. Details on the appropriate syntax, and the options involved, can be found in Xilinx UG615: Spartan-6 Libraries Guide for HDL Designs, around page 274 ("RAMB16BWER"). You can ...


5

My guess is that there will be no difference. However, the results will depend greatly on the specific tool set you use as well as the target architecture (FPGA? ASIC?). By the time the tools get to the placement and routing steps they have long forgotten what your RTL looked like. In fact, the gates themselves may have been optimized away or the logic ...


4

Synthesis tools use various techniques to optimize the results, particularly with regard to placement. Some of those techniques, such as simulated annealing, make use of random numbers. Apparently, the random number generator is seeded with a fixed value when you launch the tool, but additional randomness is incorporated on successive runs. The bottom line ...


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