23
votes
Accepted
Why do non-synthesizable commands even exist in VHDL?
Those parts of VHDL exist for use in testbenches.
Being able to simulate a VHDL design under a VHDL testbench is an essential step in the VHDL development process.
Verification is proving a design ...
- 22.2k
18
votes
Accepted
FPGA register initialization
the FPGA synthesizer ignores these code parts completely?
Both Quartus (Altera/Intel) and Vivado/ISE (Xilinx) respect initial statements for synthesis (as do some others). You can use them to set ...
- 64.7k
15
votes
How to get a FPGA design that will definitely work on actual hardware
At a place I worked there were two camps of FPGA designers. One camp I called simulate, simulate, simulate or s cubed. The other camp was all about design.
The s cubed guys used a simulator like ...
- 77.8k
13
votes
Accepted
Detect the first rising edge of 3 input signals
You could use the circuit below with 3 D flip-flops and one 3-input AND gate.
You would also need to use the reset input of the flip-flops to bring the output back to zero (not indicated in the ...
- 2,197
11
votes
Why is synthesis so slow compared to compilation?
Compiling a kernel is a process which simply takes some source code and then linearly converts and links it as machine code.
Synthesis is a process which involves making multiple iterations of the ...
- 8,505
8
votes
Accepted
Handling inferred clocks during RTL Synthesis
You have added an FPGA tag, so I will answer from an FPGA perspective. If you are creating an ASIC or using some other flow, a different answer might apply.
1. Why ...
- 1,977
8
votes
Synthesis of Analog Circuits With a Desired Input and Output Characteristic
As pointed out @Tim Williams, this can be done simply, something like this.
Just adjust some components ...
But as you are using some DSP, this can be done also with simple software.
- 11.9k
7
votes
Accepted
Can a flip flop possibly work at over 800MHz?
Here is a D flip-flop spec'ed to operate at 40 Gbps. Setup and hold times are advertised as 4 ps. It consumes only about 750 mW.
These are manufactured with a SiGe process, although I don't know ...
- 128k
7
votes
Accepted
Why isn't this decoder being inferred as a LUT?
The RTL schematic shows you how it has interpreted your code. As you can see, it has the exact combination of AND gates and multiplexers that your code describes. ...
- 1,977
7
votes
Accepted
Partially associated formal cannot have actual OPEN in VHDL under Vivado
In VHDL, you cannot connect an individual element of a port to open. You must connect either the whole port to open, or connect ...
- 1,977
7
votes
Accepted
Synthesis of Analog Circuits With a Desired Input and Output Characteristic
To be clear, Fourier transforms do not apply to a DC transfer function, at least not profitably, in any context I can think of offhand. But we can apply other kernels to approximate or solve for a ...
- 26.8k
6
votes
How to get a FPGA design that will definitely work on actual hardware
Main things are:
Careful coding to avoid non-synthesizable structures
Minimize logic levels for better timing performance (make logic between registers as simple as possible)
test, test, test to ...
- 40.8k
6
votes
Detect the first rising edge of 3 input signals
Put each input on the set of an SR latch, and AND all the outputs together.
- 29.6k
6
votes
Synthesis rules for this procedural assignment (combinational circuit)
a = -a ;
a = a << 1 ;
Both these statements inside the combinatorial always block are not valid for synthesis at ...
- 10.8k
6
votes
Accepted
Can a digital designer beat synthesis tools?
Can a digital designer beat synthesis tools?
The synthesizer will likely always find an optimal solution for any reasonably simple Boolean function.
To be useful, HDL needs to run on some sort of ...
- 11.9k
6
votes
Accepted
Will FPGA synthesis tools ignore unused modules?
Unlike software where the compiler will sometimes keep code around that isn't actually called (particularly for things like libraries), this isn't the case for HDL designs. This is because HDL isn't &...
- 40.8k
6
votes
Accepted
Are the initial conditions for reg and wires synthetizable in Verilog?
Yes, initial values for reg are supported in Artix (and the majority of other) FPGAs. Opinions differ on whether it's a good idea to rely on it; there are some ...
- 2,301
5
votes
How to get a FPGA design that will definitely work on actual hardware
All your synthesizable code needs to be expressable as:
LUTs
Flip-flops
Vendor-specific primitives
Vendor-specific primitives are either instantiated explicitly, or generated by the vendor's wizard,...
- 8,439
5
votes
Accepted
VHDL optimization
My guess is that there will be no difference. However, the results will depend greatly on the specific tool set you use as well as the target architecture (FPGA? ASIC?).
By the time the tools get to ...
- 31.3k
5
votes
Accepted
Parametric bit-width assignment in Verilog
You were very close. The proper syntax is as follows:
CODE <= {BUS_WIDTH{1'b0}};
CODEreg <= {BUS_WIDTH{1'b0}};
Refer to IEEE ...
- 6,770
5
votes
Accepted
Non-constant index in a synthesizable Verilog deserializer
While it is not possible to use a variable index inside the standard [:] parts select, because you could declare different widths, there is the indexed part select ...
- 64.7k
5
votes
Can a digital designer beat synthesis tools?
For logic crunching of combinatorial HDL into combinatorial gates i.e. LUTs, then the synthesis tool will produce exactly the same firmware.
I've actually done the exercise you're describing and much ...
- 22.2k
4
votes
Blocking vs Non Blocking Assignments
1) I am not able to understand how the changing from blocking to non-blocking
The example code posted was for a combinatorial block, changing all blocking (=) to ...
- 1,180
4
votes
Blocking vs Non Blocking Assignments
The blocking vs non blocking assignment is a crucial concept and you have difficulty to implement them correctly because you have not understood the conceptual difference.
I have attached a slide of ...
- 862
4
votes
Accepted
Synthesisable alternative to the wait statement in VHDL
A clock and a counter.
Where you enter the wait state, you set the counter, then decrement it on every clock cycle, and when it reaches zero, you exit the wait state.
- 12.4k
4
votes
Accepted
Introduce delay on a single bit signal w.r.t. input clock
That is not a correct way to add a delay. This technique will lead to missed pulses, or wrong pulse length. Bascially, here, you're just synchronizing your output every 4 cycles.
To make a proper ...
- 16k
4
votes
Accepted
Is there any tool that can create a logic circuit equivalent to some Verilog code?
Just about any FPGA/PLD tool should be able to do that.
In the somewhat obsolete Xilinx ISE Project Navigator that I currently have open the first item under Synthesize is "View RTL schematic". ...
- 6,902
Only top scored, non community-wiki answers of a minimum length are eligible