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Use this tag when you have questions regarding synthesizable code and the behaviour of the synthesis tool. Synthesis can be either for FPGA or ASIC.

Transform a high-level design description (e.g. VHDL or Verilog) into a design implementation in terms of logic gates, typically by using a computer program called a synthesis tool. Some synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs.

Reference: https://en.wikipedia.org/wiki/Logic_synthesis