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10 votes
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What is the use of 'import' in SystemVerilog?

There is an interesting article here regarding the difference between import and `include when it comes to packages. I'm going ...
Tom Carpenter's user avatar
9 votes
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Nonblocking ++ equivalent in SystemVerilog

There is no non-blocking equivalent to the ++ operator. It has been suggested for the next revision of the standard.
dave_59's user avatar
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9 votes
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Verilog - Use integer constant to define signal width

Although the terminology sounds similar, there are big differences between a constant expression and a const variable. A constant expression is an expression whose ...
dave_59's user avatar
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8 votes
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Apostrophe in Verilog array assignment

SystemVerilog has the array assignment operator '{...} in addition to the concatenation operator {...}. Concatentation is for ...
Tom Carpenter's user avatar
8 votes
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Why can't you mix edge signals with level signals in SystemVerilog for synthesis?

Your example, and the standard negedge rstN do not have the same behaviour. Let's see why. I assume we are trying to make a positive edge clocked D-FF with an ...
Tom Carpenter's user avatar
7 votes
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Is it possible to use conditional statements to modify parameters at compile time in Verilog?

You can use the conditional operator condition ? true_expression : false_expression as long as everything within the expression is a parameter or literal constant. ...
dave_59's user avatar
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7 votes

Are there any free simulators for SystemVerilog?

All the versions of Modelsim: Student Edition (SE), the FPGA simulation tools released with Intel Quartus (IE), MicroSemi Libero (ME), and Xilinx Vivado (XE), support all SystemVerilog constructs with ...
dave_59's user avatar
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7 votes
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Is it necessary to declare reg before assignment in Verilog?

The LRM says in 1800-2017 section 6.5 Nets and variables that you must declare data(signals) before using them. There are such things as implicitly declared nets, but that does not apply here. There ...
dave_59's user avatar
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7 votes

Is (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?

They are equivalent. The width of all operands get extended to the size of the largest operand before any operation occurs. As long as the width of one of BC or AD is 16 bits wider than the value ...
dave_59's user avatar
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7 votes
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Multiple driver error for SystemVerilog initial value

Get rid of the end before the else. The compiler is confused about where the first if ends. ...
hacktastical's user avatar
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7 votes
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How can I fix delay between Instruction and Program Counter?

What you've encountered there are the problems that come with instruction pipelining. I assume that you're going to synthesize your processor for running it on an FPGA at some point, so removing the ...
Jonathan S.'s user avatar
6 votes
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Is there a "standard" way to verify HDL of a state machine?

Verification is a huge part of the design process; in a complex design, it would not be unusual to spend as much time, or even more time on verification than you do on the actual design. That being ...
scary_jeff's user avatar
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6 votes
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Is it possible to create a reusable full subtractor in SystemVerilog?

Sure, but you don't need to. Just write a - b wherever you would instantiate the full substractor. Your code will be more readable and synthesis hasn't had ...
DonFusili's user avatar
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6 votes
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Is it a good practice to define TRUE/FALSE constants in SystemVerilog?

A good practice is creating a package with a set of global parameters used by your project that you can import. Putting them in a package avoids namespace ...
dave_59's user avatar
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6 votes
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Why don't I see the clocking block input skew in waveforms?

There is nothing wrong; the simulation behaves as expected. The clocking block applies the 4ns delay to the output as expected and as seen in your waves. However, the clocking block does not apply ...
toolic's user avatar
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6 votes
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Addition of two hex numbers in Verilog gives wrong result

You’ve declared your constants as 8 bit values with the 8’ prefix. So 0x63 + 0x63 = 0xc6 which is correct. If you want a 32 bit result then use the 32’ prefix on your constants.
Kartman's user avatar
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6 votes
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Warning about unused input pin with Verilog 2D array declaration

col is declared as as 3-bit input port. This means it can have 8 possible values: 0-7. You are using this as the index into ...
toolic's user avatar
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5 votes
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Net type, variable type, data type and data objects

No wire is not a data type; it is a net type. SystemVerilog has some confusing implicit declaration defaults to be backward compatible with Verilog. When you ...
dave_59's user avatar
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5 votes

How to write 'a signal should never have certain value before it attains some other value' in SystemVerilog assertion?

property p; @(posedge clk) (A != 2) until (A == 1); endproperty assert property (p);
dave_59's user avatar
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5 votes
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Combinational loop in Verilog/SystemVerilog

a+=1 is just a short-hand for a=a+1. They both are equivalent. There is no combinational loop in both cases. ...
Mitu Raj's user avatar
  • 11k
5 votes

Is it necessary to declare reg before assignment in Verilog?

TL;DR You should always declare your variables before trying to use them. When you declare your variable first, both ModelSim and Quartus will happily know what it is. However if you try to use a ...
Tom Carpenter's user avatar
5 votes
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How do we initialise unpacked arrays in Verilog?

Remember, b[7:0] means an array of eight 1-bit numbers. In your example you are trying to initialise it with a single 8-bit number, which is not the same thing. ...
Tom Carpenter's user avatar
5 votes

Verilog for loop - genvar vs int

This is somewhat historical. Prior to SystemVerilog, you had to declare the loop index separately, and prior to Verilog-2001, you had to enclose a generate-for loop with the keywords ...
dave_59's user avatar
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5 votes

What adder does the use of the operator + synthesize to when used in creating an adder module?

Depends on the tool and the target architecture. It will sometimes for example infer a DSP48 (Xilinx) but that is not a given and sometimes you will get something built in the fabric (Which generally ...
Dan Mills's user avatar
  • 17.6k
5 votes

Why do we declare the inputs of our design as reg in testbench and outputs as wire?

Inputs are declared as reg and outputs as wire only in Verilog. In SystemVerilog, we use ...
Shashank V M's user avatar
  • 2,331
5 votes

Verilog code testbench error: port is not a port of dut

According to the section "12.3.1 Port definition" in one of the revisions of the Verilog standard, a module includes [ list_of_port_declarations ] ; with ...
megasplash's user avatar
5 votes

Multiple driver error for SystemVerilog initial value

You can write a statement inside the combinational block like this: ...
Shashank V M's user avatar
  • 2,331
5 votes
Accepted

Basic question on intra-assignment delay in Verilog

Intra-assignment delays in a Verilog always block should NEVER be used (NEVER!). There is no known hardware that behaves like this intra-assignment delay using blocking assignments. If I could take ...
Cliff Cummings's user avatar
5 votes

What is difference between reg in Verilog code and reg while writing testbench code?

There is no difference. A reg is a signal that can be assigned to in a procedural block (i.e. an always or ...
The Photon's user avatar
  • 131k
5 votes
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Parametric bit-width assignment in Verilog

You were very close. The proper syntax is as follows: CODE <= {BUS_WIDTH{1'b0}}; CODEreg <= {BUS_WIDTH{1'b0}}; Refer to IEEE ...
toolic's user avatar
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