24
votes
What is the difference between testing and verification?
Was an ASIC Design Verification Engineer at Qualcomm. In the most simple way I can explain it:
Testing: Making sure a product works, after you've created the product (think QA).
Verification: Making ...
- 675
16
votes
Difference between >> and >>> in verilog?
It is not similar to ==/===, if the left hand operand is signed then >>> performs ...
- 1,140
16
votes
Why delays cannot be synthesized in Verilog?
Synthesizing means somehow converting what you have described (in Verilog here) into real hardware.
Now in your Verilog you say that you have a 50ns delay. Ok, but now, in term of hardware, how would ...
- 5,763
10
votes
Difference between >> and >>> in verilog?
According to IEEE1800-2012 >> is a binary logical shift, while >>> is a binary arithmetic shift.
Basically, ...
- 342
10
votes
Accepted
What is the use of 'import' in SystemVerilog?
There is an interesting article here regarding the difference between import and `include when it comes to packages. I'm going ...
- 57.6k
8
votes
How to remove this warning in Verilog?
If you know that you don't need the signals, ignore the warning. But why would you declare a 9 bit bus whilst only needing one signal? That's bad practice.
Generally about such warning:
You should ...
- 868
8
votes
Accepted
Nonblocking ++ equivalent in SystemVerilog
There is no non-blocking equivalent to the ++ operator. It has been suggested for the next revision of the standard.
- 6,284
7
votes
Accepted
systemverilog structure initialization with default = '1
Yes, it is legal SystemVerilog. Refer to IEEE Std 1800-2012 § 10.9 Assignment patterns
my_struct s = '{default:'1, c:0}; is equivalent to ...
- 4,130
7
votes
Is (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?
They are equivalent. The width of all operands get extended to the size of the largest operand before any operation occurs. As long as the width of one of BC or AD is 16 bits wider than the value ...
- 6,284
7
votes
Accepted
Multiple driver error for SystemVerilog initial value
Get rid of the end before the else. The compiler is confused about where the first if ends.
...
- 40.9k
7
votes
Accepted
Verilog - Use integer constant to define signal width
Although the terminology sounds similar, there are big differences between a constant expression and a const variable.
A constant expression is an expression whose ...
- 6,284
7
votes
Accepted
How can I fix delay between Instruction and Program Counter?
What you've encountered there are the problems that come with instruction pipelining. I assume that you're going to synthesize your processor for running it on an FPGA at some point, so removing the ...
- 7,228
6
votes
Why delays cannot be synthesized in Verilog?
Porting my answer from SO. Which focuses on why it is impractical to synthesise absolute delays
When synthesising clock trees the synthesis tool balances these by adding delays so that all nodes ...
- 1,140
6
votes
What is the difference between testing and verification?
In my book Verification is ensuring that what you have designed "does the job" - i.e., you have a set of things the "device" needs to perform, and verification ticks those off on the list.
Testing, ...
- 55.5k
6
votes
Accepted
Is it possible to use conditional statements to modify parameters at compile time in Verilog?
You can use the conditional operator condition ? true_expression : false_expression as long as everything within the expression is a parameter or literal constant.
...
- 6,284
6
votes
Are there any free simulators for SystemVerilog?
All the versions of Modelsim: Student Edition (SE), the FPGA simulation tools released with Intel Quartus (IE), MicroSemi Libero (ME), and Xilinx Vivado (XE), support all SystemVerilog constructs with ...
- 6,284
6
votes
Accepted
Apostrophe in Verilog array assignment
SystemVerilog has the array assignment operator '{...} in addition to the concatenation operator {...}.
Concatentation is for ...
- 57.6k
6
votes
Accepted
Is it possible to create a reusable full subtractor in SystemVerilog?
Sure, but you don't need to.
Just write
a - b
wherever you would instantiate the full substractor. Your code will be more readable and synthesis hasn't had ...
- 1,059
6
votes
Accepted
Why don't I see the clocking block input skew in waveforms?
There is nothing wrong; the simulation behaves as expected. The clocking block applies the 4ns delay to the output as expected and as seen in your waves.
However, the clocking block does not apply ...
- 2,856
5
votes
Accepted
using C libraries inside verilog
Well, you might be able to do it for accelerating your simulation, but it is not possible to synthesize this and put it on an FPGA. Verilog code is a hardware description language that describes the ...
- 39.8k
5
votes
Accepted
What is wrong with following Verilog code where I am trying to pass a one-dimensional array?
There seems to be a problem in the port declaration for module sorting_three. You're trying to pass an argument that can't exist.
Looks like module ...
- 13.5k
5
votes
Declare queue in verilog
Queues are SystemVerilog and they are not synthesizable. Queues are intended only to be used in simulation for verification and behavioral modeling.
If you want a queue functionality to synthesize, ...
- 4,130
5
votes
Accepted
Net type, variable type, data type and data objects
No wire is not a data type; it is a net type. SystemVerilog has some confusing implicit declaration defaults to be backward compatible with Verilog.
When you ...
- 6,284
5
votes
How to write 'a signal should never have certain value before it attains some other value' in SystemVerilog assertion?
property p;
@(posedge clk) (A != 2) until (A == 1);
endproperty
assert property (p);
- 6,284
5
votes
Accepted
Combinational loop in Verilog/System verilog
a+=1 is just a short-hand for a=a+1. They both are equivalent.
There is no combinational loop in both cases.
...
- 10.6k
5
votes
Accepted
Is it necessary to declare reg before assignment in Verilog?
The LRM says in 1800-2017 section 6.5 Nets and variables that you must declare data(signals) before using them. There are such things as implicitly declared nets, but that does not apply here. There ...
- 6,284
5
votes
What adder does the use of the operator + synthesize to when used in creating an adder module?
Depends on the tool and the target architecture.
It will sometimes for example infer a DSP48 (Xilinx) but that is not a given and sometimes you will get something built in the fabric (Which generally ...
- 16.2k
5
votes
Multiple driver error for SystemVerilog initial value
You can write a statement inside the combinational block like this:
...
- 2,431
5
votes
Is it a good practice to define TRUE/FALSE constants in SystemVerilog?
A good practice is creating a package with a set of global parameters used by your project that you can import. Putting them in a package avoids namespace ...
- 6,284
5
votes
Accepted
Basic question on intra-assignment delay in Verilog
Intra-assignment delays in a Verilog always block should NEVER be used (NEVER!). There is no known hardware that behaves like this intra-assignment delay using blocking assignments. If I could take ...
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