24
Was an ASIC Design Verification Engineer at Qualcomm. In the most simple way I can explain it:
Testing: Making sure a product works, after you've created the product (think QA).
Verification: Making sure a product works BEFORE you've created it.
They're both testing, just that verification is more complicated because you have to figure out a way to test ...
14
Synthesizing means somehow converting what you have described (in Verilog here) into real hardware.
Now in your Verilog you say that you have a 50ns delay. Ok, but now, in term of hardware, how would you convert this into actual hardware?
If you are using an FPGA, how would you actually build your 50ns delay using the available FPGA resources (LUT, ...
13
It is not similar to ==/===, if the left hand operand is signed then >>> performs sign extension.
reg signed [9:0] b = 10'sb11_0101_0101;
reg signed [9:0] a_signed;
reg [9:0] a_unsigned;
always_comb begin
a_signed = b >>> 2;
a_unsigned = b >> 2;
end
Result:
#a_signed 1111010101
#a_unsigned 0011010101
Example on ...
9
Not aware of any tool that will automatically do the conversion. You could do it by hand or write your own script. Here is a list of common SystemVerilog to Verilog-2001 (or vice-versa)
Easy conversions:
always_comb --> always @*
always_latch --> always @*, may want to add a synthesis directive for latch
always_ff --> always
int --> integer or reg signed [...
9
There is an interesting article here regarding the difference between import and `include when it comes to packages. I'm going to attempt to summarise it here.
When you `include a file, it is basically saying take the contents of that file and paste it at the location of the include statement. This is effectively the same behaviour as #include in C/C++.
...
8
First off, it is a common practice that parameters are upper case. When reading code this helps identify constants from variables. For arrays, refer to IEEE Std 1800-2012 § 7.4 Packed and unpacked arrays.
Packed means all the bits can be accessed at once or sliced
Unpacked means each index must be individually selected.
The following have the same ...
8
According to IEEE1800-2012 >> is a binary logical shift, while >>> is a binary arithmetic shift.
Basically, arithmetic shift uses context to determine the fill bits, so:
arithmetic right shift (>>>) - shift right specified number of bits, fill with value of sign bit if expression is signed, otherwise fill with zero,
arithmetic left ...
8
If you know that you don't need the signals, ignore the warning. But why would you declare a 9 bit bus whilst only needing one signal? That's bad practice.
Generally about such warning:
You should definitely worry about it!
This warning means that you're not using signals that you've declared so synthesis -- being the clever thing that it is -- optimised ...
6
My usual technique is to implement a 2-stage synchronizer to bring the asynchronous input in to the clock's timing domain, and then use one more flip-flop as the edge detector. Depending on the logic you use in the last statement, you can detect rising edges, falling edges or both.
module control
(
output logic pcEn,
input clock, ready
);
reg r1,...
6
DPI doesn't have special print commands. You can use regular C printf() or std::cout << "Your Message Here" << std::end. Some reasonable tutorials can be found with your preferred search engine with [systemverilog dpi] as your search term.
If you want to be lazy, you can keep #include <vpi_user.h> in your DPI files to keep using vpi_printf(...
6
In my book Verification is ensuring that what you have designed "does the job" - i.e., you have a set of things the "device" needs to perform, and verification ticks those off on the list.
Testing, though, is making sure that the things the "device" does are done right. You have a set of functions, and you test each function making sure that function ...
5
You want to match the right hand side width with the declaration width to avoid tool warnings?
First use a 1-bit wide zero constant, this will be expanded using the Verilog expansion rules, which will give you an appropriate width zero:
wire [width-1:0] a_net = 1'b0;
If that generates a simulator/synthesiser warning your tools are outside of the Verilog ...
5
When using Port Order connections, the ports are connected in the order declared by the module, and any unused ports are left unconnected (Z).
Instantiating by Port Name connections helps avoid this kind of problem.
Your code is interpreted as this:
D_ff dff_instance (
.q ( q ), // first port
.qbar ( ~q ), // second port
...
5
SystemVerilog included a range of new features intended to improve verification productivity and the most significant are probably:
Object Oriented programming
Constrained randomsation
Functional verification in simulation is entirely a software problem, so by including classes the verification community acquired all of the productivity gains of ...
5
Porting my answer from SO. Which focuses on why it is impractical to synthesise absolute delays
When synthesising clock trees the synthesis tool balances these by adding delays so that all nodes receive the clock at the same time, so it would seem that the synthesis tool does have the ability to add delays.
However when ASICs are manufactured there is a ...
5
There seems to be a problem in the port declaration for module sorting_three. You're trying to pass an argument that can't exist.
Looks like module stimulus must be a test bench for module sorting_three, since module stimulus does not have any input or output ports.
Test bench module stimulus declares memory row_data as a 1-dimensional array of 4-bit ...
5
Well, you might be able to do it for accelerating your simulation, but it is not possible to synthesize this and put it on an FPGA. Verilog code is a hardware description language that describes the functionality and interconnections of your design. It is not executed like a program, it is synthesized into the equivalent of a schematic diagram.
You ...
5
Yes, it is legal SystemVerilog. Refer to IEEE Std 1800-2012 § 10.9 Assignment patterns
my_struct s = '{default:'1, c:0}; is equivalent to my_struct s = '{a:16'hFFFF, b:16'hFFFF, c:16'h0000};
my_struct s = '{default:0, c:'1}; is equivalent to my_struct s = '{a:16'h0000, b:16'h0000, c:16'hFFFF};
Your version Vivado might not have implemented the default:...
5
Queues are SystemVerilog and they are not synthesizable. Queues are intended only to be used in simulation for verification and behavioral modeling.
If you want a queue functionality to synthesize, then you must create an fixed sized array and manage the pointer(s).
SystemVerilog and Verilog have features only usable in simulation. They language itself ...
5
No wire is not a data type; it is a net type. SystemVerilog has some confusing implicit declaration defaults to be backward compatible with Verilog.
When you write the following in Verilog:
wire w;
it's the same as this following in SystemVerilog:
wire logic w;
This means w is a net with a 4-state data type (0,1,x or z). And the wire kind of net means ...
5
a+=1 is just a short-hand for a=a+1. They both are equivalent.
There is no combinational loop in both cases.
a will be simply driven 1 in both cases. Synthesiser usually flags this as warning or info.
5
The LRM says in 1800-2017 section 6.5 Nets and variables that you must declare data(signals) before using them. There are such things as implicitly declared nets, but that does not apply here. There are also different rules when referencing names that have a . (period) in them. But both of those other situations contribute to why Verilog has this rule.
4
change const to parameter
parameter int primeArray [11] = '{3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37};
...
genvar n;
for (n = 0; n < 11; n++) begin : gen_loop
PrimeCounter #(primeArray[n]) counter ( .match(match[n]), .* );
end
working example here
I added initial $display("%m id:%0d",id); into my PrimeCounter, output is as follows:
# dut....
4
Coming from a an ASIC (hardware) design background, there are three important terms: validation, verification, and test. The earlier answers generally talk about one or two of these terms, but don't clearly contrast all three in the way I would. Here's the way I understand them:
Validation: does the specification (often a C model) meet market or customer ...
4
The terms keep changing with the time, but one has to start looking at the definitions adopted by the standardization group of SystemC TLM2.0. The work led to the definition of two coding styles:
Loosely-timed (temporal decoupling, only sufficient timing detail to boot O/S and run multi-core systems)
Approximately timed (cycle approximate, cycle count ...
4
1) I am not able to understand how the changing from blocking to non-blocking
The example code posted was for a combinatorial block, changing all blocking (=) to non-blocking (<=) may affect simulation but will not affect synthesis. This results in a RTL to gate level mismatch. It is an incorrect place to use the non-blocking assignment, do not use it ...
4
With variable as an input, the compiler can't assign a constant value to transitionConst, as you've discovered.
You should declare your module like this, and then override the OFFSET parameter as a parameter to each invocation of the module. localparam variables may not be overriden, but parameter can be as shown. You can also supply a default value to the ...
4
You can use the conditional operator condition ? true_expression : false_expression as long as everything within the expression is a parameter or literal constant.
localparam transitionConst = (transitionConst <= maxLength) ? x + y + z + offset : transistionConst - maxLength;
You can also use functions to define parameters, as long as all the function ...
4
Your approach is extremely wasteful of resources. You don't need to keep adding up the numbers in the middle of the FIFO. Instead, you add the numbers to an accumulator as they go in, and you subtract them back out of the accumulator when they come out of the FIFO.
This requires just two adders, regardless of the amount of data, and a dual-port block RAM ...
4
You have to look at the BNF to understand how code is parsed. Indenting makes code easier to read, but is meaningless for the compiler
conditional_statement ::= // from A.6.6
[ unique_priority ] if ( cond_predicate ) statement_or_null
{ else if ( cond_predicate ) statement_or_null }
[ else statement_or_null ]
And a begin/end ...
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