10
votes
Accepted
What is the use of 'import' in SystemVerilog?
There is an interesting article here regarding the difference between import and `include when it comes to packages. I'm going ...
- 64.7k
9
votes
Accepted
Nonblocking ++ equivalent in SystemVerilog
There is no non-blocking equivalent to the ++ operator. It has been suggested for the next revision of the standard.
- 7,787
7
votes
Accepted
Is it possible to use conditional statements to modify parameters at compile time in Verilog?
You can use the conditional operator condition ? true_expression : false_expression as long as everything within the expression is a parameter or literal constant.
...
- 7,787
7
votes
Are there any free simulators for SystemVerilog?
All the versions of Modelsim: Student Edition (SE), the FPGA simulation tools released with Intel Quartus (IE), MicroSemi Libero (ME), and Xilinx Vivado (XE), support all SystemVerilog constructs with ...
- 7,787
7
votes
Accepted
Is it necessary to declare reg before assignment in Verilog?
The LRM says in 1800-2017 section 6.5 Nets and variables that you must declare data(signals) before using them. There are such things as implicitly declared nets, but that does not apply here. There ...
- 7,787
7
votes
Accepted
Apostrophe in Verilog array assignment
SystemVerilog has the array assignment operator '{...} in addition to the concatenation operator {...}.
Concatentation is for ...
- 64.7k
7
votes
Is (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?
They are equivalent. The width of all operands get extended to the size of the largest operand before any operation occurs. As long as the width of one of BC or AD is 16 bits wider than the value ...
- 7,787
7
votes
Accepted
Multiple driver error for SystemVerilog initial value
Get rid of the end before the else. The compiler is confused about where the first if ends.
...
- 51k
7
votes
Accepted
Verilog - Use integer constant to define signal width
Although the terminology sounds similar, there are big differences between a constant expression and a const variable.
A constant expression is an expression whose ...
- 7,787
7
votes
Accepted
How can I fix delay between Instruction and Program Counter?
What you've encountered there are the problems that come with instruction pipelining. I assume that you're going to synthesize your processor for running it on an FPGA at some point, so removing the ...
- 15.5k
6
votes
Accepted
Is there a "standard" way to verify HDL of a state machine?
Verification is a huge part of the design process; in a complex design, it would not be unusual to spend as much time, or even more time on verification than you do on the actual design. That being ...
- 1,977
6
votes
Accepted
Is it possible to create a reusable full subtractor in SystemVerilog?
Sure, but you don't need to.
Just write
a - b
wherever you would instantiate the full substractor. Your code will be more readable and synthesis hasn't had ...
- 1,067
6
votes
Accepted
Is it a good practice to define TRUE/FALSE constants in SystemVerilog?
A good practice is creating a package with a set of global parameters used by your project that you can import. Putting them in a package avoids namespace ...
- 7,787
6
votes
Accepted
Why don't I see the clocking block input skew in waveforms?
There is nothing wrong; the simulation behaves as expected. The clocking block applies the 4ns delay to the output as expected and as seen in your waves.
However, the clocking block does not apply ...
- 6,830
6
votes
Accepted
Addition of two hex numbers in Verilog gives wrong result
You’ve declared your constants as 8 bit values with the 8’ prefix. So 0x63 + 0x63 = 0xc6 which is correct. If you want a 32 bit result then use the 32’ prefix on your constants.
- 6,090
6
votes
Accepted
Warning about unused input pin with Verilog 2D array declaration
col is declared as as 3-bit input port. This means it can have 8 possible values: 0-7. You are using this as the index into ...
- 6,830
5
votes
Declare queue in verilog
Queues are SystemVerilog and they are not synthesizable. Queues are intended only to be used in simulation for verification and behavioral modeling.
If you want a queue functionality to synthesize, ...
- 4,280
5
votes
Accepted
Net type, variable type, data type and data objects
No wire is not a data type; it is a net type. SystemVerilog has some confusing implicit declaration defaults to be backward compatible with Verilog.
When you ...
- 7,787
5
votes
How to write 'a signal should never have certain value before it attains some other value' in SystemVerilog assertion?
property p;
@(posedge clk) (A != 2) until (A == 1);
endproperty
assert property (p);
- 7,787
5
votes
Accepted
Combinational loop in Verilog/SystemVerilog
a+=1 is just a short-hand for a=a+1. They both are equivalent.
There is no combinational loop in both cases.
...
- 10.8k
5
votes
Is it necessary to declare reg before assignment in Verilog?
TL;DR You should always declare your variables before trying to use them.
When you declare your variable first, both ModelSim and Quartus will happily know what it is. However if you try to use a ...
- 64.7k
5
votes
Verilog for loop - genvar vs int
This is somewhat historical. Prior to SystemVerilog, you had to declare the loop index separately, and prior to Verilog-2001, you had to enclose a generate-for loop with the keywords ...
- 7,787
5
votes
What adder does the use of the operator + synthesize to when used in creating an adder module?
Depends on the tool and the target architecture.
It will sometimes for example infer a DSP48 (Xilinx) but that is not a given and sometimes you will get something built in the fabric (Which generally ...
- 17.4k
5
votes
Why do we declare the inputs of our design as reg in testbench and outputs as wire?
Inputs are declared as reg and outputs as wire only in Verilog. In SystemVerilog, we use ...
- 2,289
5
votes
Verilog code testbench error: port is not a port of dut
According to the section "12.3.1 Port definition" in one of the revisions of the Verilog standard, a module includes [ list_of_port_declarations ] ; with ...
- 412
5
votes
Multiple driver error for SystemVerilog initial value
You can write a statement inside the combinational block like this:
...
- 2,289
5
votes
Accepted
Basic question on intra-assignment delay in Verilog
Intra-assignment delays in a Verilog always block should NEVER be used (NEVER!). There is no known hardware that behaves like this intra-assignment delay using blocking assignments. If I could take ...
5
votes
What is difference between reg in Verilog code and reg while writing testbench code?
There is no difference.
A reg is a signal that can be assigned to in a procedural block (i.e. an always or ...
- 128k
5
votes
Accepted
Parametric bit-width assignment in Verilog
You were very close. The proper syntax is as follows:
CODE <= {BUS_WIDTH{1'b0}};
CODEreg <= {BUS_WIDTH{1'b0}};
Refer to IEEE ...
- 6,830
5
votes
What can procedural statements do that assignment statements cannot do in Verilog?
I assume you are trying to compare a continuous assign statement with procedural assignment inside an always block.
...
- 7,787
Only top scored, non community-wiki answers of a minimum length are eligible