7

They are equivalent. The width of all operands get extended to the size of the largest operand before any operation occurs. As long as the width of one of BC or AD is 16 bits wider than the value being shifted, then what you wrote is mathematically equivalent to \$(BC + AD)×2^{16} = BC×2^{16}+ AD×2^{16}\$ If the width of the largest operand is not wide ...


6

There is no non-blocking equivalent to the ++ operator. It has been suggested for the next revision of the standard.


6

Sure, but you don't need to. Just write a - b wherever you would instantiate the full substractor. Your code will be more readable and synthesis hasn't had difficulties with this construct since the 90s.


5

The LRM says in 1800-2017 section 6.5 Nets and variables that you must declare data(signals) before using them. There are such things as implicitly declared nets, but that does not apply here. There are also different rules when referencing names that have a . (period) in them. But both of those other situations contribute to why Verilog has this rule.


5

Depends on the tool and the target architecture. It will sometimes for example infer a DSP48 (Xilinx) but that is not a given and sometimes you will get something built in the fabric (Which generally has a semi dedicated carry chain up a column, so this is quicker then you might expect). Why do you even care as long as it meets timing? If you want a ...


4

SystemVerilog has the array assignment operator '{...} in addition to the concatenation operator {...}. Concatentation is for packed arrays - basically you combine multiple signals into a single bus. wire [7:0] a = {4'd7, 4'd14}; You can nest concatenation operators too. The following assigns the same value to b as was assigned to a in the previous example. ...


4

Inputs are declared as reg and outputs as wire only in Verilog. In SystemVerilog, we use logic for 4-state simulation and bit for 2-state simulation. In Verilog, inputs are declared as reg because they are variables which store values during simulation. The value is stored in the inputs of type reg till it is overwritten by some other value. The datatype ...


3

The design is partitioned into 2 parts - one for combinational logic and another for sequential logic. In the sequential logic part, an always_ff block is used. Counter is an internal signal used to store the values and it gets incremented on the positive edge of the clock. Counter is a binary counter, and it has a modulus of 2 raised to the power of its ...


3

Remember, b[7:0] means an array of eight 1-bit numbers. In your example you are trying to initialise it with a single 8-bit number, which is not the same thing. For Verilog, you have to initialise each element in the array one by one: b[0] = 1'b0; b[1] = 1'b0; b[2] = ... You could also use a for-loop and localparam to initialise it, by storing the packed ...


3

Your problem is the rules for Verilog expression bit length say that operands get extended to their context determined lengths before applying the operators. In the expression: ~(sub_ton[11:0])+1 The +1 is really +32'sd1, a signed 32 bit decimal number. sub_ton[11:0] gets 0-padded to 32 bits, then the bitwise negation happens, followed by the addition. ...


3

TL;DR You should always declare your variables before trying to use them. When you declare your variable first, both ModelSim and Quartus will happily know what it is. However if you try to use a variable before declaring it, all bets are off. If you don't declare a variable at all, its existence will be inferred. Quartus usually makes them up reasonably ...


3

This is somewhat historical. Prior to SystemVerilog, you had to declare the loop index separately, and prior to Verilog-2001, you had to enclose a generate-for loop with the keywords generate/endgenerate module top; generate genvar i; for (i=0; i<4 ; i = i + 1) begin integer j; reg [i+1:0] value; initial for(j=0; j<4; j =...


3

The inner single quote before the 1 is a numeric literal fill. The '0, '1, 'z, and 'x literals will be extended to fill the width of whatever context they are used in. The outer single quote before the { means that this is an assignment pattern to an array or struct. Assignment patterns require a value for every element of the array or struct, which can be ...


3

Here's another method: x <= {2'b01, {width_x-2{1'b0}}}; Or you can use bit shifting if width_x is relatively small: x <= 1 << (width_x - 2);


3

There is no requirement for inout ports to be placed only in the top level. That being said, an FPGAs typically don't support internal tri-state buffers, so the use of them in internal modules is not necessarily representing a bidirectional signal. In your case where you wish to feed a tristate signal from a lower level module up to the top level, this is ...


3

You are combining two true but mutually exclusive ideas. You certainly can set all of your gate delays to zero and you will have the world's fastest processor, but it will only exist in your simulation. If you want to manufacture a processor you won't be able to set the gate delays arbitrarily. You will have to use the manufacturer's process parameters to ...


3

There is no difference in the two examples you wrote. You can even make is simpler: module counter ( input wire clk, clr, output reg [3:0] q ); always @(posedge clk or posedge clr) begin if (clr) q<= 4'b0000; else q<= q+ 1'b1; end endmodule


2

The ports on your submodule will always exist whether you use them on not. If you don't connect an input/inout port of a submodule it will be connected to some default value by the synthesis tool. This is usually 'b0 for an input, or 'bz for an inout port, but could be anything. Leaving inputs unterminated is not ideal. If you don't connect an output port ...


2

Assuming tb.gen_block_mem is a generate block, you'll have to put the covergroup in another generate block for(genvar id=0;id<MY_P;id++) begin : cg_block covergroup CG; cp1 : coverpoint tb.gen_block_mem[id].var_x[3:0]; endgroup : CG CG cg = new; end : cg_block


2

The IEEE Std 1800-2017, section 20.7 Array query functions, describes all that you need: module tb; logic x [0:3][7:0] ; initial begin for (int i=1; i<=$dimensions(x); i++) begin $display; $display($size (x, i)); $display($left (x, i)); $display($right(x, i)); $display($low (x, i)); $display($high (x,...


2

Debouncer This debouncer assumes that its input is synchronised to the clock. The output will only change state when the input has been in the opposite state for N clock cycles, i.e. a form of hysteresis to produce a kind of low pass filter. The counter only counts when the input and output differ, thus reducing switching losses when the input equals the ...


2

Inline initialization is not good, even for the b signal. A commercial tool I use for ASIC synthesis ignores those initializations and throws warnings. If b is a constant, the below would be better (still not ideal). logic b; assign b = 1; I experienced failures in formal equivalence checking (RTL vs. synthesis netlist) as well, so I avoid inline ...


2

Yes, it is called the conditional compile construct `ifdef or `ifndef. For examples module foo(...); `ifdef SYNTHESIS // code to be synthesised `else // code not to be synthesized `endif endmodule See https://stackoverflow.com/questions/58996919/how-to-determine-that-synthesis-is-done-in-quartus


2

I want to find out what adder(ripple adder, carry look ahead adder etc.) does the operator + in verilog synthesize to when used in design an adder module. The answer will depend on the synthesis target, and potentially also what the optimiser is optimising for. In my experience on Altera FPGAs it will normally be a ripple carry adder, BUT said ripple carry ...


2

You missed assign keyword for that concurrent statement - assign mul3_op[0] = d [0] ;


2

There are actually different concepts. When you use AND gate it means that you have two ( or more) "one bit" inputs and the output is zero unless all of them are high. On the other hand the operator "&" means bitwise "and". It means that if you have two ,let's say, four bits binary numbers "a" and "b", &...


2

Vivado Synthesis Guide guide mentions about this issue in page 260: Targeting SystemVerilog for a Specific File By default, the Vivado synthesis tool compiles *.v files with the Verilog 2005 syntax and *.sv files with the SystemVerilog syntax. To target SystemVerilog for a specific *.v file in the Vivado IDE, right-click the file, and select Source ...


2

This is simply out = (32'd1 << $countones(in)) - 32'd1; Note: increase 32 to the size of your vector.


2

It would really help to show the code you wrote as your attempt and how it is supposed to iterate, as well as the exact error, but I think you just need a logical shift left. logic [7:0] reg8; logic [11:0] reg12; int iterator; // goes from 0 to 7 // each iteration reg12 = reg8 << 11-iterator;


2

Shashank's answer is good. I would like to add that in a more sophisticated testbench, all DUT pin signals could be declared as wires since you might choose to have another module drive your DUT inputs (i.e., a bus-functional model). If all of your stimulus is driven from the testbench directly, then it makes sense to declare DUT input signals as reg (or ...


Only top voted, non community-wiki answers of a minimum length are eligible