12
votes
Accepted
VHDL: What is correct way to model open collector output for FPGA?
FPGAs have tri-state outputs :
sda <= 'Z' when dout='1' else '0';
There are also sometimes optional internal pull-ups, but they are not meant to drive ...
- 3,337
11
votes
Accepted
How do I protect myself when testing a PCB that involves an AC line?
An isolation transformer will make it safe to touch live, but definitely not live and neutral simultaneously.
Another option is a RCD (residual current device). I purchased a sensitive one which ...
- 68.7k
7
votes
Accepted
Temporary PCB connections for testing
Headers are pretty cheap and make a lot of sense over a wide range of quantities, down to 1 piece. A 5 x 2 header takes up very little space, even less in 2mm pitch. The connections usually end up ...
- 367k
6
votes
How do I protect myself when testing a PCB that involves an AC line?
You are missing the very first thing I'd use, which is a isolation transformer. The next most useful device is the variac. Your redundant fuse and circuit breaker are just silly.
When using both a ...
- 310k
5
votes
VHDL: What is correct way to model open collector output for FPGA?
Note that FPGA design tools sometimes provide a specific open-drain primitive in their library. E.g. in Quartus II you can write
...
- 25.4k
5
votes
Why do we declare the inputs of our design as reg in testbench and outputs as wire?
Inputs are declared as reg and outputs as wire only in Verilog. In SystemVerilog, we use ...
- 2,374
5
votes
Accepted
Why does this file give me "syntax error: I give up." in verilog program?
Your apostrophe chars are the problem
$dumpfile(“example.vcd”);
should be
$dumpfile("example.vcd");
And for all ...
- 2,459
4
votes
Accepted
This model of a D-Flip flop with Enable not working as expected
In your first code sample, you have a low active reset (if (~Reset) D <= 0). And in the testbench you hold Reset low for most ...
- 125k
4
votes
Xilinx's ISE (GSR): The initial block adds a delay of 100 time units to simulation
I think what you are seeing is the result of the internal GSR signal falling at t=100ns. This signal prevents the flip flops from changing state while it is asserted. It's sort of like an internal ...
- 40.6k
4
votes
How do I implement the clock into this testbench?
The problem is with this block:
always@(clk) begin
clk = 1;
#20;
clk = 0;
#20;
end
It will only run when clk is high, since you have @(clk) as ...
- 5,914
4
votes
Verilog Code test bench problem
According to the section "12.3.1 Port definition" in one of the revisions of the Verilog standard, a module includes [ list_of_port_declarations ] ; with ...
- 392
3
votes
VHDL Algorithm state machine output
Some problems with your code:
1) Testbench: You are not initializing the reset signal or driving it to a valid state during the simulation. Fix this.
2) Testbench: Your clock period is 40 ns but ...
- 1,041
3
votes
Accepted
getting outputs in simulation as all high impedance. topic: restoring algorithm for binary division
Your testbench isn't connecting any signals to the DUT outputs (q, r, busy, ready, count). You declared the signals in the testbench but didn't make the connections.
how would i do that ? ...
- 31k
3
votes
Usage of "initial" in Verilog module description
It is a common misconception that initial blocks cannot ever be synthesised.
In fact, for FPGAs, they can in most cases be synthesised. In fact the use of initial ...
- 61.9k
3
votes
Usage of "initial" in Verilog module description
1/ Is it bad practice?
It is perfectly fine and often done in test benches. But I assume that is not what you where alluding to. I would prefer to say it is rarely done. The reason is that it can not ...
- 14.2k
3
votes
Verilog counter does not work
When I run your code on 2 different simulators, I get compile warnings about port size differences for d and qd. Your counter ...
- 4,706
3
votes
Accepted
VHDL Clock Divider Problem
I've rounded up all the good advice from the comments into an answer.
Clock Strobe
Generates a slower strobe from a faster clock.
...
- 850
3
votes
Accepted
Problem with reading a .csv file into a Verilog module
Try inserting commas ,
j = $fscanf(f,"%b,%b,%b",r1,r2,r3);
- 7,252
2
votes
Accepted
I need to derive a lower frequency clock from the main clock and sample it in verilog
Your problem is probably this line:
assign result = reg2[0];
Because earlier you declared
output reg [3:0] result;
Nets ...
- 125k
2
votes
Writing synthesizable testbenches
A general approach is to use more abstracted tests as you progress up the stack in terms of design complexity. Yes, you need to trust the tools (and the checking tools like logical equivalence proofs),...
- 3,723
2
votes
Load image into VHDL testbench
You might consider writing a VHDL package to read and write some simple image format, such as XPM which, being text, is probably easier to handle than binary files such as bmp,jpg etc.
Just use GIMP ...
- 66.9k
2
votes
Load image into VHDL testbench
No. In the past I have made a Matlab script to convert an image into a format the is easy to read into a testbench such as an rgb image stored in a simple format like hexadecimal rgb stored one pixel ...
- 410
2
votes
What options exist to verify Avalon-MM slave component?
I found that there are basically four options:
Include the CPU (NIOS-II) itself in the simulation.
Use an existing "open core" CPU design.
Use a "bus functional model" (BFM).
Create my own ...
- 167k
2
votes
Electrical gremlins under high Amp draws
Lamp ignition on a HID lamp is electrically very noisy, being as it involves very high voltage pulses for arc ignition.
I would expect the problem here to be RF pickup by the USB leads during lamp ...
- 17k
2
votes
If constraints in SystemVerilog
constraint my_constraint { if (b==0 && c==0) d==1; else d==0;}
- 7,252
2
votes
Accepted
How to model devices external to FPGA in a testbench?
If you are to use an external SRAM in your FPGA platform, then you need not only the "cycle accurate", but also (mostly) "timing-accurate" model, if you want something to work. The timing depends on ...
- 38.6k
2
votes
Accepted
Ultracapacitor initial voltage drop during discharging
Using only the ESR from the datasheet (ideal wires...):
Current is practically zero before discharging and jumps to 10A, hence the drop. Initial linear discharge is expected due to constant current.
...
- 8,357
2
votes
Verilog Testbench - wait for specific number of clock cycle edges
Put your @(posedge clk) in a for loop:
for (i=0; i<60000; i=i+1)
@(posedge clk) ;
- 14.2k
Only top scored, non community-wiki answers of a minimum length are eligible