12

FPGAs have tri-state outputs : sda <= 'Z' when dout='1' else '0'; There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor. VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs. You can write sda <='H'; in the test-bench to ...


11

An isolation transformer will make it safe to touch live, but definitely not live and neutral simultaneously. Another option is a RCD (residual current device). I purchased a sensitive one which trips at 10mA leakage current to ground, which is safer than the 30mA one which protects the whole house. You will still get a large jolt if you touch the wires, ...


7

Headers are pretty cheap and make a lot of sense over a wide range of quantities, down to 1 piece. A 5 x 2 header takes up very little space, even less in 2mm pitch. The connections usually end up free of flux so they don't crud up the mating connector. For really high volume, you can use a fixture with spring-loaded 'pogo' pins which can be cheaper per ...


6

You are missing the very first thing I'd use, which is a isolation transformer. The next most useful device is the variac. Your redundant fuse and circuit breaker are just silly. When using both a variac and a isolation transformer, put the variac in front of the isolation transformer. This is because many common isolation transformers are toroids that ...


5

Note that FPGA design tools sometimes provide a specific open-drain primitive in their library. E.g. in Quartus II you can write LIBRARY altera; USE altera.altera_primitives_components.all; sda: opndrn PORT MAP ( a_in => sda_wire, a_out => sda_pin ); This shouldn't make any difference on a bidir IO pin, but it may make a difference if you need to ...


4

Some problems with your code: 1) Testbench: You are not initializing the reset signal or driving it to a valid state during the simulation. Fix this. 2) Testbench: Your clock period is 40 ns but your testbench waits for 20 ns to change the inputs. This is faster than the system can respond to changes. Probably not what you want to do for basic behavior ...


4

I think what you are seeing is the result of the internal GSR signal falling at t=100ns. This signal prevents the flip flops from changing state while it is asserted. It's sort of like an internal reset. I'm not sure if you can change the GSR behavior in modelsim. But what you can do is simply add a 100 ns delay before starting the clock signal so you avoid ...


4

Inputs are declared as reg and outputs as wire only in Verilog. In SystemVerilog, we use logic for 4-state simulation and bit for 2-state simulation. In Verilog, inputs are declared as reg because they are variables which store values during simulation. The value is stored in the inputs of type reg till it is overwritten by some other value. The datatype ...


4

According to the section "12.3.1 Port definition" in one of the revisions of the Verilog standard, a module includes [ list_of_port_declarations ] ; with the following syntax: list_of_port_declarations ::= ( port_declaration { , port_declaration } ) | ( ) port_declaration ::= {attribute_instance} inout_declaration | {...


4

Your apostrophe chars are the problem $dumpfile(“example.vcd”); should be $dumpfile("example.vcd"); And for all the literals, such as, #5 t_x = 1’b0; t_y= 1’b0; they should be #5 t_x = 1'b0; t_y= 1'b0;


3

It is a common misconception that initial blocks cannot ever be synthesised. In fact, for FPGAs, they can in most cases be synthesised. In fact the use of initial blocks is quite common. You can use them to set the power-on value of structures such as RAMs, ROMs, and registers. This is not bad practice at all, and helps with both simulation and synthesis ...


3

Your testbench isn't connecting any signals to the DUT outputs (q, r, busy, ready, count). You declared the signals in the testbench but didn't make the connections. how would i do that ? everywhere i search for a testbench example i do not see 'the connection' you are talking about. You do it the exact same way you connected the inputs: // instantiate ...


3

In your first code sample, you have a low active reset (if (~Reset) D <= 0). And in the testbench you hold Reset low for most of the simulation. As expected this results in D being 0. In your second code sample you have a high-active reset (if (reset) q <= 0 ) which will naturally behave differently.


3

When I run your code on 2 different simulators, I get compile warnings about port size differences for d and qd. Your counter declares them as 8-bit wide, but you connect 1-bit signals to them. If you don't get warnings, try it on edaplayground. In test_b, declare them as 8-bit: module test_b; reg clk,clear,load,up_down; reg [7:0] d; wire [7:0] qd; ...


3

The problem is with this block: always@(clk) begin clk = 1; #20; clk = 0; #20; end It will only run when clk is high, since you have @(clk) as the sensitivity list at the beginning of the block. A more typical way to generate your clock is this: initial clk = 0; always #20 clk = ~clk; Actually, though, your original code might work fine ...


3

I've rounded up all the good advice from the comments into an answer. Clock Strobe Generates a slower strobe from a faster clock. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ClockStrobe is generic ( CLOCK_PERIOD : time := 20 ns; STROBE_PERIOD: time := 2 ms ); port ( reset : in ...


2

A general approach is to use more abstracted tests as you progress up the stack in terms of design complexity. Yes, you need to trust the tools (and the checking tools like logical equivalence proofs), but for a whole-fpga design (a) there won't be space for a testbench, and (b) exhaustive coverage will take a long time. A good approach is to use exhaustive ...


2

You might consider writing a VHDL package to read and write some simple image format, such as XPM which, being text, is probably easier to handle than binary files such as bmp,jpg etc. Just use GIMP or other image processing software to export the images you want to XPM, and import your testbench's results.


2

No. In the past I have made a Matlab script to convert an image into a format the is easy to read into a testbench such as an rgb image stored in a simple format like hexadecimal rgb stored one pixel per line ( use the textio library to parse the file line by line). For my tests There was some assumed row/column ordering and a fixed size image. Then I run ...


2

If you are to use an external SRAM in your FPGA platform, then you need not only the "cycle accurate", but also (mostly) "timing-accurate" model, if you want something to work. The timing depends on particular memory chip and manufacturer, so the normal way is to download the model form manufacturer's site. Again, you keep repeating your questions, but ...


2

I found that there are basically four options: Include the CPU (NIOS-II) itself in the simulation. Use an existing "open core" CPU design. Use a "bus functional model" (BFM). Create my own simulatable CPU and bus master interface. I ended up using option 4. The problem with option 1 is that the full-blown CPU is complex and simulates slowly. On chips that ...


2

Lamp ignition on a HID lamp is electrically very noisy, being as it involves very high voltage pulses for arc ignition. I would expect the problem here to be RF pickup by the USB leads during lamp ignition (You may also see HDMI dropping out), cure is probably some ferrites as common mode chokes on the ballast DC connections (And maybe also on the USB ...


2

constraint my_constraint { if (b==0 && c==0) d==1; else d==0;}


2

Using only the ESR from the datasheet (ideal wires...): Current is practically zero before discharging and jumps to 10A, hence the drop. Initial linear discharge is expected due to constant current. The larger drop you see is certainly due to wires, switches etc. To be more specific, let's consider 3 steps: charging: capacitor practically reached its max....


2

I would try to use an analog mux with low on resistance such as the adg1606. https://www.analog.com/en/products/adg1606.html It has less than 8ohms resistance over most of your temperature range and likely won't have a problem in cold where the mux performance isn't specified.


2

Shashank's answer is good. I would like to add that in a more sophisticated testbench, all DUT pin signals could be declared as wires since you might choose to have another module drive your DUT inputs (i.e., a bus-functional model). If all of your stimulus is driven from the testbench directly, then it makes sense to declare DUT input signals as reg (or ...


2

Thank you for the suggestions. I used Questa performance profiler. There was an assertion within the testing environment which caused this. Because of the way it was written, the sequence it was asserting, started every cycle. As the time progressed, the simulation time and memory taken by this increased and it made the simulation slower. This in-turn had a ...


1

Wish I could comment, b/c there are a lot of syntactical issues here. You defined a type called H and then tried to assign something to the type: H(0) := v_adcValue which is illegal and may explain the first part of the error. You must define the type and then declare a variable or signal of the defined type, which can then receive assignment. It looks ...


Only top voted, non community-wiki answers of a minimum length are eligible