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18 votes
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Setup and hold time output when violated

If the flip-flop's setup time is 20 ns, it means that data has to be stable atleast 20ns before the capturing clock-edge. Similarly hold time is the amount of time, data has to remain stable after a ...
Mitu Raj's user avatar
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9 votes

Why is de-assertion of an asychronous reset a problem compared to its assertion?

The assertion timing doesn't matter because the whole point is that all the elements of the circuit enter a valid/known reset state. It generally doesn't matter what order they do it in, only that ...
Evan's user avatar
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9 votes

Setup and hold time output when violated

Your professor needs to cut back on the herbs. Since the data is changing within the setup time, and since setup time is a minimum amount of time before the clock that the data needs to be stable, it ...
Trevor_G's user avatar
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8 votes
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Attack and Release times of the Automatic Gain Control

The objective of an automatic gain control is to manipulate its gain in order to keep the output RMS signal level roughly constant despite the input level RMS value changing significantly. To do this ...
Andy aka's user avatar
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7 votes

How do I delay MOSFET turn on without slowing down the rise time?

Start with this: - And then invert the output of the OR gate. Both gates should be schmitt trigger types. The RC time constant and the schmitt trigger high and low thresholds produce the deadband ...
Andy aka's user avatar
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7 votes

Help understanding practical transistor considerations?

Welcome to the real world of EE. A lot of what we do is from experience grounded on the solid theoretical teachings. As you suspect in your first point, job number one is to nail down EXACTLY what ...
Trevor_G's user avatar
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7 votes
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What will be the real voltage along the line with a voltage source and a capacitor?

What looks like a 'line' running from your voltage source, past your resistors, to your capacitor isn't. It's a NODE. The simulator models it as a single connection point, with a single voltage. You ...
Neil_UK's user avatar
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7 votes
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Why does my counter appear to work if it fails timing closure?

Now go build 10,000 of your circuit, and test them at the FPGA's maximum rated ambient temperature and lowest specified power supply voltage. Do they all work? The timing analysis isn't telling you ...
The Photon's user avatar
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7 votes
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How to calculate the number of required flip-flop stages needed for clock-domain crossing?

The number of flip flops needed depends on three things: target MTBF requirement clock rate ‘crunchiness’ of the flip flops The latter point, ‘crunchiness’, is also called metastable hardness, and ...
hacktastical's user avatar
7 votes
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Vivado constraints wizard suggests a lot of nonsense generated clocks

The following code in alu infers a latch: ...
toolic's user avatar
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6 votes
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Cyclone V data corruption at high frequency

Since you say you met the correct functionality at 2 MHz, but not in higher frequency. It is most probably a setup/hold timing violation. Do timing analysis of the entire design for clock constraint ...
Mitu Raj's user avatar
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6 votes

How to write to a Hitachi HM628128A SRAM?

You can use either method, the two different timing diagrams in the document illustrate two different timing schemes that can be used for a write operation. My guess is they do this to facilitate ...
Voltage Spike's user avatar
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5 votes

Attack and Release times of the Automatic Gain Control

AGC being Automatic Gain Control? They're the times it takes to ramp to a gain, rather than instantly jumping causing a discontinuity in the audio, it is ramped up and down smoothly. There's a good ...
Colin's user avatar
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5 votes

Setup and hold time output when violated

If the data is stable between the setup and hold times, then the D latch manufacturer is guaranteeing that the output of the D latch will be predictable, what it says it will be in the data sheet. If ...
Neil_UK's user avatar
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5 votes

SPI interface on Xilinx FPGA, clock domains and timing constraints

The usual approach is to cross MOSI, CS and SCLK to the internal FPGA fabric clock (running at a far higher rate then the SPI bus) domain and do all the actual work there. Crossing a clock domain ...
Dan Mills's user avatar
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5 votes
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Why double synchronizer alone is not enough for multi byte transfer between two clock domains?

Transferring a single bit is simple. It has only two states, and when a transition occurs, it can only be either in the previous state or the new state. Therefore the ONLY concern is metastability, ...
Dave Tweed's user avatar
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4 votes
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Typical vs. min/max timing and voltages

Vcc typical 5V (with a minimum and maximum of 2V and 7V) ... why use Vcc = 2, 4.5, and 7 volts as its conditions Probably because the characteristics at 4.5 V are less desirable than those at 5 V. ...
Olin Lathrop's user avatar
4 votes

Setup and hold time output when violated

The output will be unknown and a simulator will reflect this by setting the output value to 'X'.
Oldfart's user avatar
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4 votes

Setup and hold time output when violated

If the input meets the setup and hold time requirements, then the output is essentially "guanranteed" to reflect the input; if it violates the setup time, the behavior is no longer guaranteed or fully ...
BobH's user avatar
  • 111
4 votes
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How to use/create a real time clock to use with specialized?

CD4060 IC binary counter + Osc follow Xtal Osc design Use Q15 = divide by 2^15= 32,768 = 1 Hz Xtal 32,768 kHz + discrete RC parts or MEMS OSC XO 32.7680KHZ CMOS SMD more CD4060/4040's and gates ...
Tony Stewart EE75's user avatar
4 votes
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Passing input on one pin of FPGA straight out to another output pin for monitoring

Unconstrain the output (set a false path) and the timing violation will go away. In Vivado you put these in the .xdc file for your design. More about that here: https://forums.xilinx.com/t5/Timing-...
hacktastical's user avatar
4 votes

Analysis of two D flip-flop designs based on D latches

The timing constraints for the D Flip-Flop constructed using D latches to work are: \$t_{ccq(initiator)} >= t_{hold(follower)}\$ \$t_{ccq(initiator)}\$ represents the clock-to-q contamination delay ...
Shashank V M's user avatar
  • 2,331
4 votes
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Do more logic gates in series mean more slowing of the output result?

It's definitely the case that frequency can increase with simpler logic. A 3 GHz processor has 333 picoseconds to complete every operation. A few extra picoseconds of delay means lower operating ...
Matt's user avatar
  • 624
4 votes

Do more logic gates in series mean more slowing of the output result?

The basic idea is correct. Less gates mean less propagation delay from the input to the output of the network. Given that 99% of the logic these day is synchronous this propagation delay is the upper ...
Lorenzo Marcantonio's user avatar
4 votes
Accepted

Why does metastability occur if data changes during setup and hold time?

The fundamental problem is that the input is continuous, and the output is discrete. In synchronous systems, this is further compounded by the fact that the decision has to be made in a finite time. ...
Neil_UK's user avatar
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4 votes
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Why is a reset with asynchronous assert safe?

The first circuit that you have shown is a case of RDC (Reset Domain Crossing) as the launching flop and capturing flops are in two different reset domains. As you said, if you assert the async reset ...
Mitu Raj's user avatar
  • 11k
4 votes

How to write to a Hitachi HM628128A SRAM?

You can use either one, whichever fits with your system doing the write.
Justme's user avatar
  • 159k
3 votes

Timing warnings for functional model

Setup and hold timing checks only make sense with post-layout information. A century ago, you could do timing analysis without layout structural information because the the device delays were ...
dave_59's user avatar
  • 8,630
3 votes

Synchronize Outputs of Separate FPGAs Within 1ns

Is there any more sound approach to this problem? Yes!! Put both of the FPGA functions into a single device. Trying to maintain determinism to with 1ns for separate devices is close to a pipe ...
Michael Karas's user avatar
3 votes

FPGA: intentional delays through manual placement/routing

What I've done in a recent design is to multiply up the clock frequency and use a clocked delay. That can get me granularity in the sub-5ns region with a cheap FPGA. This document from Lattice ...
Spehro Pefhany's user avatar

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