Skip to main content
25 votes

Are there any microcontrollers that do not require an external clock source?

Many (most?) MCU's have an internal oscillator that can be used as the clock. Typically there will be a configuration that is held in non-volatile memory to set the clocking mode. The actual method ...
Kevin White's user avatar
  • 33.8k
21 votes
Accepted

Why does the race hazard theorem work?

As others have pointed out, mathematically the statements are exactly the same, and the additional term is "redundant". It would also be "redundant" for me to copy their mathematical proofs here. ...
jbord39's user avatar
  • 4,390
20 votes

Is there a microcontroller with zero interrupt jitter?

You are approaching this from the wrong direction. You shouldn't have a specification which says "I need such mcu to measure times between two events with precision up to 1 cycle". You ...
Lundin's user avatar
  • 21.1k
15 votes
Accepted

Why am I Seeing A Weird "Notch" on the Data Line For Some Logical 1s?

Thanks for everyone's help. I believe Bruce Abbott has given the correct answer. I'm posting from my bed and I cannot test it yet until tomorrow, but The analysis below is confirmed, when he mentioned ...
比尔盖子's user avatar
  • 7,218
12 votes
Accepted

Why microcontroller takes many clock cycles to start up with PLL clock source?

Deeper interpretation: The PLL is actually producing clock cycles during that whole time. The problem is that until it achieves "lock", the clock cycles may at times be too short to allow the CPU to ...
Dave Tweed's user avatar
  • 175k
12 votes
Accepted

How can the RMW instructions on PIC14 take a single cycle?

You get a first clue in the datasheet where it states DC - 20 MHz oscillator / clock input DC - 200 ns instruction cycle A 20 MHz clock has a cycle time of 50 ns, that's only 1/4th of the 200 ns ...
kruemi's user avatar
  • 3,334
11 votes

Are there any microcontrollers that do not require an external clock source?

The Microchip PIC range of chips (or at least some of them) can use their own internal oscillator, instead of an external clock.
Simon B's user avatar
  • 19.5k
10 votes

Why does the race hazard theorem work?

Proof by Boolean algebra: A x B + A' x C [Left-hand side] = A x B x 1 + A' x C x 1 [Unsimplify AND with true] = A x B x (1 + C) + A' x C x (1 + B) [True OR anything] = A x B x 1 + A x B x C + A' x 1 ...
Nayuki's user avatar
  • 278
10 votes

Are there any microcontrollers that do not require an external clock source?

Just look for internal oscillator in the documentation or features on an MCU. There are drawbacks and positives to using an internal oscillator Chances are, your favorite MCU has an internal RC ...
Voltage Spike's user avatar
  • 84.6k
9 votes

Why is there a maximum time for length of write pulse to write on an EEPROM?

I assume your question relates to parallel EEPROMs. The Write pulse (time) is a minimum specification and typically has no upper bound. In other words the time specified limits the speed of writing (...
Jack Creasey's user avatar
  • 21.8k
9 votes
Accepted

How can I implement a very simple asynchronous DRAM controller?

There are complete schematics for the IBM PC/XT in the IBM Personal Computer XT technical reference manual (Appendix D), which you may be able to find on line. The problem here is that, given a ...
David Moews's user avatar
8 votes

Why does the race hazard theorem work?

Consider the LHS by itself: A x B + A' x C If both B and C are true in this statement, does the condition of A make any difference to the result? No - because either (A x B) or (A' x C) will be ...
brhans's user avatar
  • 14.7k
8 votes

Why am I Seeing A Weird "Notch" on the Data Line For Some Logical 1s?

Ensure that you have adequate decoupling capacitors on all your ICs. A 100nF ceramic from power to ground on each IC keeping its leads as short as possible and a low ESR electrolytic say 100uF on the ...
RoyC's user avatar
  • 10.1k
8 votes

When using PWM, what is the purpose of having two complimentary square waves on the same channel?

Imagine you drive something in a PUSH-PULL configuration; then, PWMH can drive the high-side switch, whereas PWML drives the low side switch. Many of these PWM controllers even have a dead-time ...
Marcus Müller's user avatar
8 votes

Is there a microcontroller with zero interrupt jitter?

I believe some of the simpler PIC series have constant interrupt latency. For example, the ancient PIC16F84 has latency listed as 3.25 Tcy (or 13 clock cycles). Unless your interrupt request is ...
Spehro Pefhany's user avatar
8 votes

Why specify a maximum pulse width for reset pin?

When enabled the RESET button on the EVAL board simply grounds the /RESET pin (schematic available at the manufacturer's website). I see no specific instruction to limit the time of your finger on the ...
Spehro Pefhany's user avatar
7 votes

How can I implement a very simple asynchronous DRAM controller?

Your question is complicated enough that I'm not even sure what your actual problem is, but I'll try! The "cleanest" 6502-based DRAM design I could find is from the Commodore PET 2001-N. It has a ...
pipe's user avatar
  • 14.5k
7 votes

Rigol DS1074 oscilloscope shows very wrong timing

Looks like a bug to me. I reproduced it on my 1054z using an Arduino with an LED blinking program. This is the signal with 12M memory depth acquired at 500ms timescale, and then expanded at 200 ms ...
Sredni Vashtar's user avatar
6 votes

RTC - is it worth it?

Firstly, a real time clock is not what you want. A real time clock is designed to give you the current time, as in year, month, day, hour, minute, second etc. It usually has a battery, so it can keep ...
Jack B's user avatar
  • 12.2k
6 votes

Electrical Device Up-time

First, the current sensors. You don't even need to tap into the wires - a properly chosen coil placed next to a "live" mains wire (say, taped to the supply cable) with AC will have current induced in ...
SF.'s user avatar
  • 1,212
6 votes

SDRAM: Why CAS latency is configurable

Inside the SDRAM chip, the actual CAS latency requirement is a combinatorial time delay, independent of the external interface's clock period. It may help to think of it as an old-fashioned ...
Dave Tweed's user avatar
  • 175k
6 votes
Accepted

ADC Chip Timing Question

Here's a good clue: - And, if you look at the value for \$t_4\$ it is quoted here: - So, a new data bit is available between 0 and 40 ns of the falling edge of SCLK. This means you can't rely on the ...
Andy aka's user avatar
  • 465k
6 votes

Is there a microcontroller with zero interrupt jitter?

One way would be to not use interupts for measuring the time at all. Certain processors like the SAMD series from Microchip have an event system, where peripherals can trigger events which lead to ...
Steven's user avatar
  • 161
6 votes

Is there a microcontroller with zero interrupt jitter?

Input Capture Many, many microcontrollers have an "input capture" feature. A timer runs freely at a fixed frequency. When an external signal happens, the timer value is copied to a ...
Matt Timmermans's user avatar
6 votes

STM32 writing to SD card using FATFS sometimes takes longer than normally

SD card are not a realtime medium. You need to buffer the writes to it. Internally the SD card prefers full blocks. It then applies wear leveling. You have no control over this. So sometimes the ...
Jeroen3's user avatar
  • 23.1k
5 votes

What's the standard procedure of DDR4 training?

There isn't a standard procedure defined; JEDEC says its up to each manufacturer to determine the most appropriate way to carry it out. But there is a guidance document produced by Micron that gives ...
Finbarr's user avatar
  • 5,836
5 votes
Accepted

Op-Amp settling time in bits

A 10-bit binary number can take on 210 = 1024 values. Therefore, if you want something to settle "within 10 bits," you're saying that it needs to settle to within 1 part in 1024: \$\frac{1}{1024} = 0....
Dave Tweed's user avatar
  • 175k
5 votes

Cascaded flip-flops and shift register timing

Edge triggered FFs have set-up and hold time requirements. Only data that was present before the clock triggered, will have satisfied the set-up time, and thus be "registered". Since (if ...
Math Keeps Me Busy's user avatar
5 votes

Cascaded flip-flops and shift register timing

To understand it, consider first a gated D-Latch which is level sensitive which means that the input is applied to the output as long as the gate (E) is active, otherwise the last state is maintained: ...
Paul Ghobril's user avatar
  • 2,906
5 votes
Accepted

How does Asynchronous DRAM perform self-timing

Asynchronous DRAM is not self-timed at all. The DRAM controller must meet all of the timing requirements specified in the DRAM datasheet, or the operation will simply fail in some way. Even with ...
Dave Tweed's user avatar
  • 175k

Only top scored, non community-wiki answers of a minimum length are eligible