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20

As others have pointed out, mathematically the statements are exactly the same, and the additional term is "redundant". It would also be "redundant" for me to copy their mathematical proofs here. You can also easily verify the statements are equivalent by making a 8 row truth table for the three inputs combinations. A B C A*B + A'*C ...


19

Many ages ago not long after the first caveman whittled a piece of silicon into a transistor, they learned how to make a bunch of transistors on the same hunk of silicon. This led to all kinds of things that we consider as always having been around, like the 741 opamp, 7805 regulator, and 2N2222 transistor. Yes, these things actually had beginnings. They ...


14

False paths are timing paths that will never really be exercised in the final design. Suppose you are designing a 4-bit counter and it turns out that there is a very slow delay path when incrementing from 12 to 13. If your design always resets the counter whenever the count equals 9 then that slow path will never be seen in the actual design. You label the ...


14

A edge-triggered latch (flipflop) ideally samples the data line instantaneously on one of the edges of the clock. However, nothing is truly instantaneous, so the data must be valid for some finite amount of time around the clock edge. The time it must be fixed before the clock edge is called the setup time, and the time it must be fixed after the clock ...


13

Thanks for everyone's help. I believe Bruce Abbott has given the correct answer. I'm posting from my bed and I cannot test it yet until tomorrow, but The analysis below is confirmed, when he mentioned the word "refresh", I think the problem is already solved. I knew how Z80 refreshes the memory, but completely forgot about it in the previous days. ......


12

There's always some propagation delay through the flip-flop. It's often called "clock-to-Q" delay. That means your inputs are captured on the edge, and you outputs change on the same edge, but just a few nanoseconds later. This few nanoseconds delay is enough (if your flip-flops are designed with "zero hold time" as they are in most FPGAs) that the changes ...


12

Deeper interpretation: The PLL is actually producing clock cycles during that whole time. The problem is that until it achieves "lock", the clock cycles may at times be too short to allow the CPU to operate correctly, as the VCO control voltage swings both above and below the target value before settling down. So what this specification is really telling ...


11

WaveDrom is a free and open source online digital timing diagram rendering engine that uses JavaScript, HTML5 and SVG to convert WaveJSON input text description into SVG vector graphics.


11

A NOP usually takes 1 instruction cycle. The PIC12F675 seems to divide the clock by four for an instruction cycle: "One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 \$\mu\$s." (datasheet p. 71) So a 20MHz clock will give you delay of 200 ns (4/20 MHz)...


10

Advancing timing is a practice common to electric motors and internal combustion engines. The purpose is to increase efficiency. In other words to maximize the power out for a given power in. In electric motors, the amount of torque produced in relation to the rotor field vector with respect to the stator field vector is given by: \$\tau = \tau_{max}~sin~\...


9

Proof by Boolean algebra: A x B + A' x C [Left-hand side] = A x B x 1 + A' x C x 1 [Unsimplify AND with true] = A x B x (1 + C) + A' x C x (1 + B) [True OR anything] = A x B x 1 + A x B x C + A' x 1 x C + A' x B x C [Distribute] = A x B + A x B x C + A' x C + A' x B x C [Simplify AND with true] = A x B + A' x C + A x B x C + A' x B x C [Rearrange terms] = A ...


9

I assume your question relates to parallel EEPROMs. The Write pulse (time) is a minimum specification and typically has no upper bound. In other words the time specified limits the speed of writing (bits/bytes/words per second), but the chips will operate at any lower write rate. For example here is the datasheet for the 26C64 write timing: Notice there ...


8

A false path is a path that does exist in the design but does not play a part in the operation, so it's not necessary to include it in the timing analysis. There could be various reasons for this being the case, but since the timing analysis tool usually doesn't know (although there are some tools which can detect them) which paths may be used or not, you ...


8

Consider the LHS by itself: A x B + A' x C If both B and C are true in this statement, does the condition of A make any difference to the result? No - because either (A x B) or (A' x C) will be true, producing a result of true. So now looking at the RHS, the first 2 AND terms are simply a duplicate of the LHS, and the 3rd AND term represents what we ...


8

Ensure that you have adequate decoupling capacitors on all your ICs. A 100nF ceramic from power to ground on each IC keeping its leads as short as possible and a low ESR electrolytic say 100uF on the breadboard across the power rails.


7

High temperature implies more thermal noise and random collisions of electrons, thus device resistance goes up and electron mobility goes down. If resistance goes up then the RC constant(s) across the device nodes will be higher and speed will be lower, as speed is inversely related to RC. edit: to address 2nd comment From 'CMOS, Cirucit Design, Layout, ...


7

"Process" in this case refers to the manufacturing process at the plant where they make the FPGA. It's a measure of the statistical variability of the physical characteristics from chip-to-chip as they come off the line. This includes everything from mask alignment to etching times to doping levels. These things affect electrical parameters such as sheet ...


7

FPGAs don't actually have "gates" per se. They typically have Look-Up Tables (LUTs). LUTs are typically implemented using SRAMs. For instance, Spartan 3 FPGAs use 16-bit SRAMs; that is, four address inputs produce one output signal. "Programming" is done by loading the SRAM with a bit pattern representing the truth table, such that for e.g. 2-input XOR, ...


7

555 timers are used for timing.. i can save you the effort of typing and direct you to a good page with some examples to try out. doctronics 555 timer page


7

It takes a lot of LUTs to build a large mux. For example, if you have 6-input LUTs, you can do a 4:1 mux in one LUT, but it takes 11 LUTs to do a 1-bit 32:1 mux. Your counter is getting replicated (as counter_reg) so that the fanout on any given bit is not excessive. (Although I'm not really sure where the 1024 comes from.) Since you don't really need "...


7

There are several advantages to this methodology that I can think of: Clock Network - Firstly you only have one clock rather than three. This means that there is less competition for global and local clock routing resources. There are usually only a small number of low-skew clock trees, so minimising usage requirements can help routing. ALM Restrictions - ...


6

Expanding on dwlech's comment. The processors have direct copper connections. The FPGAs are interconnected through programmable connections. Also the processors put critical stuff next to each other. The FPGAs also need room for the SRAM that holds the programming.


6

The voltage across a capacitance \$C\$ at time \$t\$, which was initially at voltage \$V_0\$, which is discharging through a resistance \$R\$, is given by: $$ V(t) = V_0 e^{\frac{-t}{RC}} $$ Charging a capacitor with a battery of voltage \$V_b\$ through a series resistor is similar: $$ V(t) = V_b(1-e^{\frac{-t}{RC}}) $$ From these equations, you can see ...


6

simulate this circuit – Schematic created using CircuitLab A CMOS schmitt trigger 40106 or 4093 (check the numbers) would work for this. Pick a reasonable value for C1 - 10uF, say. Calculate R so that R * C = 5 s. When the input goes high C1 will charge up. At about 2/3 of supply voltage NOT1 output will switch low and NOT2 will switch high. Q1 will ...


6

Firstly, a real time clock is not what you want. A real time clock is designed to give you the current time, as in year, month, day, hour, minute, second etc. It usually has a battery, so it can keep track of time when the device is switched off, and will be much more complicated than a basic timing device. You want to measure relative time, not absolute ...


6

First, the current sensors. You don't even need to tap into the wires - a properly chosen coil placed next to a "live" mains wire (say, taped to the supply cable) with AC will have current induced in it if considerable (typical for running appliances) current flows through the wire. The values are well within readout range of common ADC inputs, making ...


6

There are complete schematics for the IBM PC/XT in the IBM Personal Computer XT technical reference manual (Appendix D), which you may be able to find on line. The problem here is that, given a strobe line which is activated upon a memory read or write, you wish to generate RAS, CAS and a control line (call it MUX) for the address multiplexer. For ...


6

Inside the SDRAM chip, the actual CAS latency requirement is a combinatorial time delay, independent of the external interface's clock period. It may help to think of it as an old-fashioned asynchronous DRAM chip "wrapped" in a synchronous interface. Since the bus master (CPU) can choose the interface clock speed, it makes sense to also allow it to ...


6

Imagine you drive something in a PUSH-PULL configuration; then, PWMH can drive the high-side switch, whereas PWML drives the low side switch. Many of these PWM controllers even have a dead-time functionality to guarantee that both switches aren't on simultaneously


5

I am assuming the output is 3 LEDs - if it is something that uses more current (or needs higher voltage, then you will have to buffer the outputs. The only 16:1 mux I found was 74150, which has an inverting output. If your mux has a non-inverting output then you will have to invert the inputs :) Anyway, set the counter up to count from 0 to 12, connect ...


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