# Tag Info

21

As others have pointed out, mathematically the statements are exactly the same, and the additional term is "redundant". It would also be "redundant" for me to copy their mathematical proofs here. You can also easily verify the statements are equivalent by making a 8 row truth table for the three inputs combinations. A B C A*B + A'*C ...

20

You are approaching this from the wrong direction. You shouldn't have a specification which says "I need such mcu to measure times between two events with precision up to 1 cycle". You should have a specification which says precision of +/- x (milli/micro/nano) seconds. Time units, not cycles. In my experience, many instruction sets have a fixed ...

14

Thanks for everyone's help. I believe Bruce Abbott has given the correct answer. I'm posting from my bed and I cannot test it yet until tomorrow, but The analysis below is confirmed, when he mentioned the word "refresh", I think the problem is already solved. I knew how Z80 refreshes the memory, but completely forgot about it in the previous days. ...

12

Deeper interpretation: The PLL is actually producing clock cycles during that whole time. The problem is that until it achieves "lock", the clock cycles may at times be too short to allow the CPU to operate correctly, as the VCO control voltage swings both above and below the target value before settling down. So what this specification is really telling ...

10

Proof by Boolean algebra: A x B + A' x C [Left-hand side] = A x B x 1 + A' x C x 1 [Unsimplify AND with true] = A x B x (1 + C) + A' x C x (1 + B) [True OR anything] = A x B x 1 + A x B x C + A' x 1 x C + A' x B x C [Distribute] = A x B + A x B x C + A' x C + A' x B x C [Simplify AND with true] = A x B + A' x C + A x B x C + A' x B x C [Rearrange terms] = A ...

9

I assume your question relates to parallel EEPROMs. The Write pulse (time) is a minimum specification and typically has no upper bound. In other words the time specified limits the speed of writing (bits/bytes/words per second), but the chips will operate at any lower write rate. For example here is the datasheet for the 26C64 write timing: Notice there ...

8

Consider the LHS by itself: A x B + A' x C If both B and C are true in this statement, does the condition of A make any difference to the result? No - because either (A x B) or (A' x C) will be true, producing a result of true. So now looking at the RHS, the first 2 AND terms are simply a duplicate of the LHS, and the 3rd AND term represents what we ...

8

Ensure that you have adequate decoupling capacitors on all your ICs. A 100nF ceramic from power to ground on each IC keeping its leads as short as possible and a low ESR electrolytic say 100uF on the breadboard across the power rails.

8

I believe some of the simpler PIC series have constant interrupt latency. For example, the ancient PIC16F84 has latency listed as 3.25 Tcy (or 13 clock cycles). Unless your interrupt request is synchronized with the MCU clock there will be additional +/-0.5 clock cycle. In situations where you might ask this question, usually the answer is to use hardware ...

7

An inexpensive method of measuring rise and fall time limitations of an arbitrary waveform, is to start with a square wave of a moderate frequency, and then systematically increase the frequency while keeping duty cycle constant at 50%. The average intensity of emitted light is easily measured, even by using something as basic as a CdS light-dependent ...

7

It takes a lot of LUTs to build a large mux. For example, if you have 6-input LUTs, you can do a 4:1 mux in one LUT, but it takes 11 LUTs to do a 1-bit 32:1 mux. Your counter is getting replicated (as counter_reg) so that the fanout on any given bit is not excessive. (Although I'm not really sure where the 1024 comes from.) Since you don't really need "...

7

There are several advantages to this methodology that I can think of: Clock Network - Firstly you only have one clock rather than three. This means that there is less competition for global and local clock routing resources. There are usually only a small number of low-skew clock trees, so minimising usage requirements can help routing. ALM Restrictions - ...

7

Imagine you drive something in a PUSH-PULL configuration; then, PWMH can drive the high-side switch, whereas PWML drives the low side switch. Many of these PWM controllers even have a dead-time functionality to guarantee that both switches aren't on simultaneously

7

Looks like a bug to me. I reproduced it on my 1054z using an Arduino with an LED blinking program. This is the signal with 12M memory depth acquired at 500ms timescale, and then expanded at 200 ms scale. The 'beat' is 1000 ms long. (Ok, technically it's 900ms long plus the overhead, but if I add the first part of the next train I get a nice 1000 ms sequence ...

6

Why is the resistor voltage initially equal to supply voltage? Is it because there is no voltage going across the capacitor yet? Therefore, as there is no voltage drop across the capacitor, all the voltage from the battery is across the resistor? Sum of voltages on the passive elements must add up to the supply voltage.  V_{supply}(t) = V_{switch}(t) + ...

6

simulate this circuit – Schematic created using CircuitLab A CMOS schmitt trigger 40106 or 4093 (check the numbers) would work for this. Pick a reasonable value for C1 - 10uF, say. Calculate R so that R * C = 5 s. When the input goes high C1 will charge up. At about 2/3 of supply voltage NOT1 output will switch low and NOT2 will switch high. Q1 will ...

6

Firstly, a real time clock is not what you want. A real time clock is designed to give you the current time, as in year, month, day, hour, minute, second etc. It usually has a battery, so it can keep track of time when the device is switched off, and will be much more complicated than a basic timing device. You want to measure relative time, not absolute ...

6

First, the current sensors. You don't even need to tap into the wires - a properly chosen coil placed next to a "live" mains wire (say, taped to the supply cable) with AC will have current induced in it if considerable (typical for running appliances) current flows through the wire. The values are well within readout range of common ADC inputs, making ...

6

There are complete schematics for the IBM PC/XT in the IBM Personal Computer XT technical reference manual (Appendix D), which you may be able to find on line. The problem here is that, given a strobe line which is activated upon a memory read or write, you wish to generate RAS, CAS and a control line (call it MUX) for the address multiplexer. For ...

6

Inside the SDRAM chip, the actual CAS latency requirement is a combinatorial time delay, independent of the external interface's clock period. It may help to think of it as an old-fashioned asynchronous DRAM chip "wrapped" in a synchronous interface. Since the bus master (CPU) can choose the interface clock speed, it makes sense to also allow it to ...

6

Here's a good clue: - And, if you look at the value for $t_4$ it is quoted here: - So, a new data bit is available between 0 and 40 ns of the falling edge of SCLK. This means you can't rely on the falling edge of SCLK to read valid data. Of course, if you look at $t_7$ it tells you that current data is valid for maybe 7 ns should you attempt to read it ...

6

One way would be to not use interupts for measuring the time at all. Certain processors like the SAMD series from Microchip have an event system, where peripherals can trigger events which lead to other hardware to perform different actions. Considering you want to measure the time taking for charging a Capacitor: Analog Comparator 1 (low Voltage) -> ...

6

Input Capture Many, many microcontrollers have an "input capture" feature. A timer runs freely at a fixed frequency. When an external signal happens, the timer value is copied to a register, and an interrupt is raised. Regardless of the interrupt latency, then, the interrupt handler can read the value in the register and determine the precise ...

5

It is possible to measure optical pulses of LEDs and Lasers to picosecond resolution, and it is something I do regularly as an electronics/photonics person. The trick is to work in the time domain. To give an example of this, I have seen photodiodes exhibiting bandwidths of GHz, 40 GHz is quoted by a previous answer. However, I would imagine such a ...

5

EDID is used, among other things, to query the monitor for the timings it would like. It isn't used to transmit any video information. I guess it's been so long that no one remembers, but VGA monitors back in the day had adjustments for the image location on the CRT. You could move it left or right, up or down, or scale it horizontally or vertically. More ...

5

The start bit servers two purposes, to indicate a new character is being sent and to provide a timing reference for that character. To explain why the UART protocol is what it is, let's start with a simple scheme, see why that doesn't work, then see how to modify it to make it work. You can start out trying to send data using a single signal by simply ...

5

This is more of an "extended comment" than an answer, but let me start by saying no, I don't think you can debug this issue with such a limited set of test equipment. A person who has had a lot of experience doing these designs might be able to get some clues about what's going wrong using them, but I get the impression that you're not such a person. For ...

5

Actually the CS timing is not very important -- you usually assert the CS line (bring it low) at the beginning of a bunch of transfers, and then de-assert it (bring it high) at the end. What is more important is the relationship between the clock (SCK) and the data (SI/SO). Here is a typical timing diagram for an SPI peripheral, in this case a 2AA1024 1 ...

5

1) Routing is always the dominant factor limiting timing. That is why a carry-lookahead is not really faster in FPGA, as the larger adder requires more delays which partly overcome the advantages. Your path has 6 level of logic, which is O.K. It would be very hard to put all paths below 6. However, some nets have a high fanout, which yields longer delays. ...

5

Your question is complicated enough that I'm not even sure what your actual problem is, but I'll try! The "cleanest" 6502-based DRAM design I could find is from the Commodore PET 2001-N. It has a 6502 running at 1 MHz, but the DRAM logic is clocked at 16 MHz, likely to generate all the timings. I have not analyzed the details, but the main action seems to ...

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