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What determines I2C interrupt service time after address byte ACK?

It is defined by what the MCU was doing when byte is transferred, how long it takes to notice I2C interface needs servicing, and how quickly the I2C interface is serviced and ready for next transfer. ...
Justme's user avatar
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Synchronize Outputs of Separate FPGAs Within 1ns

First of all: when these signals get deserialized again, is this timing relationship still relevant, or is there a rate matching FIFO with insertion/deletion symbols that will cause and correct more ...
Simon Richter's user avatar
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Wiring the output of a D flip-flop to its input

The general idea is that whatever combinatorial logic is in the feedback path from the FF output to input propagates much slower than the input hold time of the FF. In TTL, ECL and most any CMOS logic ...
Kuba hasn't forgotten Monica's user avatar
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Wiring the output of a D flip-flop to its input

Some elementary transformations of the D-type FF obtained using the characteristic equations of each. Each gate introduces a delay in the switching times:
Franc's user avatar
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1 vote

Wiring the output of a D flip-flop to its input

The hold time is 0ns (noted to be under nominal conditions 5V / 25°C, a hint that you might have to allow a bit more under worst-case Vcc and temperature conditions). So your logic circuit can't ...
Spehro Pefhany's user avatar
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Wiring the output of a D flip-flop to its input

Yes, it is definitely possible. It will work as long as the data setup and data hold times and propagation delays in the logic are taken into account. For example wiring the inverted output directly ...
Justme's user avatar
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