# Tag Info

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SANYO 2SD1048. It’s an NPN transistor.

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The p-n-p transistors Q3-Q5 work in the so-called "reverse active mode" where the collector and emitter are swapped. The advantage of this weird connection, as far as I can remember from 80s, is that the collector-emitter voltage of the saturated transistor is lower than in the case of the conventional active mode connection. The cathode segments should be ...

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Ok, I got it. Since the switch closes at time=0s it shows the result for when the switch is closed. I had to use the current probe to see the current over time. It will go to zero after some nanoseconds.

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If you search the net for the PSpice manual you'll eventually run into this link. I don't know the name of that switch, and it looks like it's not a current, or voltage controlled one, but with the manual you should be able to find it and its usage (I don't have PSpice).

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Most transistors have a graph of SOA (safe operating area) in the datasheet. If you stay within the constraints of the SOA you (in theory anyway) won't destroy the transistor. The edges of what is permissible depend on thermal constraints for DC, on breakdown voltage and on second breakdown characteristics of the transistor. So, according to the above ...

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You mean if you keep the base current low enough so the emitter current is also limited? Sure, provided base current is low enough to keep $I_C \cdot V_{CC}$ dissipation within the device's rated power dissipation, with whatever heat sink you put on it. BJTs are current-controlled devices, they limit how much current flows through them even at a constant ...

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From the theoretical point of view, i.e if $T_J\equiv \text{const.}$, $T_A\equiv \text{const.}$ where $T_J$ and $T_A$ are respectively the junction and ambient temperature of the device and provided that the chosen $V_{CE}$ and $I_C\simeq I_E$ are not such that the maximum power rating $P_D$ is not exceeded, the answer is Yes, you do not need ...

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The really simple circuit that Neil is first talking about looks like this: simulate this circuit – Schematic created using CircuitLab (The above assumes that you have a $5\:\text{V}$ voltage source.) As mentioned, it will begin to turn on at around $12\:\text{mA}$ and be fully on after $14\:\text{mA}$, or so. So this works pretty well and is ...

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Normally you have some kind of load attached to the collector or emitter since the purpose of the transistor is to provide current or voltage gain depending upon the circuit configuration. Having said that within the constraints (see datasheet https://www.farnell.com/datasheets/115091.pdf as an example) of the device what you have stated is true e.g. don't ...

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3 X Inverter + NOR (A' + B' + C')' = A'' * B'' * C'' = A * B * C This circuit won't suffer the voltage drop issue, you can have many inputs. simulate this circuit – Schematic created using CircuitLab

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In electronics courses, they usually teach not to design circuits that depend on transistor beta having a specific value, it just won't work because each transistor you buy will have a different beta within some huge range given in the datasheet, and it will vary due to bias and temperature.

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simulate this circuit – Schematic created using CircuitLab Figure 1. One simple test. The circuit isn't very good. (a) With the bottom transistor on you'll get a potential divider between R3 and R4 of about 1/3 through the base-emitter junction of Q3 so Y1 would be about 5/3 V = 1.66. With the transistor B-E junction the simulation shows that the ...

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You can make a BJT turn on at a relatively well-defined current through a base-emitter resistor. Let's say you choose a 12 mA (halfway between 4 and 20) threshold. We want about 700 mV at that current, which needs a resistor of 700/12 = 58 ohms, 56 is the nearest preferred value. Most general purpose BJTs will be capable of sinking the balance of 8 mA ...

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The 12 V line has to have 12 V relative to some other point in your circuit. Normally this is the battery or supply negative and called 'ground' or GND and is the point from which we measure other voltages in the circuit. You would usually connect the black multimeter lead to ground when taking DC voltage measurements. simulate this circuit – ...

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but won't be more efficent to just cut de power with a transistor controlled by the MCU? Start looking at the datasheet! If standby mode consumes no more power than the leakage of your FET, then the FET is pointless. There's probably no leverage to be had here because of your 1-day interval, but a GPS receiver takes time to lock on to enough satellites to ...

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Is this the sort of thing you are after? simulate this circuit – Schematic created using CircuitLab

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As another answer says, you can't get it with your proposed design. You need a source of 10 V. But you can get that by adding a single additional resistor: simulate this circuit – Schematic created using CircuitLab Now when IN is high, you'll get about 0.2 V at the MOSFET gate. And when IN is low, you'll get about 10.4 V at the gate. There is a ...

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You can't. There's no source of 10 V that your transistor could switch. So, get a different MOSFET. Also, don't forget that for MOSFET switching, the Gate-Source voltage needs to be defined – so there has to be some common notion of potential (e.g. a common ground); your schematic doesn't have that.

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It's probably for fail-safe. There is no need of a flyback diode when the transistor is driven from the emitter as shown, by the way. The charge pump (C2/C3/D3/D3) means that even if the MCU output gets stuck high or low, the relay will drop out. Probably a square wave as Andy says. Average voltage will be about 1/2 Vcc, minus a bit because of loading. See ...

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1) why there are 2 transistors in series There's a good possibility that they are two MOSFETs wired as a solid state relay or SSR. If they are two NPN transistors as shown this may be some kind of fail-safe-under-one-fault circuit (after all you don't want one BJT to fail short circuit for possible reasons of creating a fire). If that's the case then having ...

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The MOSFET with the minimal Rdson is not always the most suitable. Those with a very low Rdson have a large Qg gate charge. It means that they need a powerful gate driver if you want to do PWM. A higher gate charge makes turn on/off slower, thus higher switching losses. The good MOSFET is the one with the lowest product: Rdson * Qg The total loss of a ...

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$A$ is the area. $I_S$ is the device's saturation current, which is proportional to $A$. The device with area $nA$ would have saturation current $n I_S$. So your second line should have been: $$= V_T \ln \left( {{I_C}\over{I_S}} \right) - V_T \ln \left( {{I_C}\over{n I_S}} \right)$$ (Note $n$ in denominator instead of numerator) The rest ...

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Ideally, a transistor should have ZERO resistance when turned on, but we don't live in an ideal world, so we're stuck with just getting the lowest resistance we can. I don't understand why would you even ask such a question, seeing that you understand that higher RdsON means more losses. OF COURSE you will try to get the lowest RdsON available. There are ...

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Your understanding of RDson and conduction loss is fine. Just know RDson varies with Vgs and increases with temperature, usually by 150% to 200% at its hottest, so you must account for this if you plan on running lots of current or hot weather. You can find the RDSon vs. temperature graph in the datasheet. But know there are switching losses if you are ...

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You need to sink current so the transistor has to be on the low side so PMOS and PNP devices are at a disadvantage. Instead, use an logic-level NMOS or NPN driven by an inverter to fix the logic levels. simulate this circuit – Schematic created using CircuitLab The TLC5940 outputs are open-collector so they can only pull the line LO, not HI. So R1 ...

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Mark - what do you want: A "demonstration" (calculation) or an explanation of this effect? Let me start with an explanation: The MILLER effect concerns the input impedance of your circuit at the base node. Here, we see two pathes: (a) into the base and (b) into the 10pF cap. The input impedance is defined as the ratio of the input signal voltage divided by ...

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Well, we have the following circuit: simulate this circuit – Schematic created using CircuitLab When analyzing a transistor we need to use the following relations: $$\text{I}_\text{E}=\text{I}_\text{B}+\text{I}_\text{C}\tag1$$ Transistor gain $\beta$: $$\beta=\frac{\text{I}_\text{C}}{\text{I}_\text{B}}\tag2$$ Emitter voltage: \text{V}_\text{BE}=\...

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It's made by ST Microelectronics based on Logo. The package is indeed DPAK (TO-252) Based on the pinout, it's not a MOSFET (either P or N). All of the ST MOSFETs in DPAK have the gate on pin 1 (lower right in the picture orientation), which makes no sense. The control line of this device is pin 3. This leaves something like a TRIAC or SCR. The DPAK ...

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Consider the following circuit. simulate this circuit – Schematic created using CircuitLab In this circuit Q1, R1, R2, RC, RE, Cin and Cout represent real components. re represents the intrinsic impedance of Q1. $re \approx \dfrac{25}{I_C}$ ohms if $I_C$ is in mA at room temperature. The usual design procedure is to pick a quiescent $I_C \... 2 The emitter resistor causes negative feedback. This can be shown using a block diagram based on the classical formulas for describing the input-output relations. It is a well-known fact that negative feedback reduces the gain factor. This is - in most cases (opamp) - a desired result of negative feedback. Note that the output current Ic is determined by the ... 3 It's useful to think of a transistor operating in three modes, cut off, linear, and saturated. When cut off, the collector current is zero. When saturated, the base current is high, and VCE is small. These are the two modes when using a transistor as a switch. You appear to be thinking of the saturated mode in your question. Wikipedia is talking about the ... 3 Gain is the output voltage change divided by the input voltage change. In the small signal hybrid pi model the collector current changes proportional to the change in base voltage (relative to the emitter) so there is a voltage change at the collector proportional to the load resistance (parallel with ro). If you add an emitter resistor, the base-emitter ... 1 In a common-emitter amplifier, think of the transistor as a variable resistor controlled by the base current ($i_b$): simulate this circuit – Schematic created using CircuitLab The output voltage (and thus the voltage gain) is determined by the voltage across the variable resistor (i.e.$V_{ce}$). Now put a resistor between the low-end of the ... 0 @vtolentino already got it right in the comments: in DC analysis all capacitors are open-circuited, it should be fairly simple to find what you want after that. I'd like to add that this BJT is not a Common-Emitter BJT, it's a Common-Base BJT because the base terminal is common to both inputs and outputs, so you're dealing with a CB NPN-BJT. 0 A "simple" amplifier made with a low current 2N2222 transistor will produce a low output level full of distortion. For 2.5W into 4 ohm speakers at fairly low distortion I would use a PAM8403 stereo class-D audio amplifier IC powered from 5V and it costs .80US at Digikey today. There are Chinese modules available that use it. 0 If you are willing to implement a switching-amplifier, H bridge, you can build 1 watt output using 3.3 volts. Will be an RFI challenge what with fast edges, but generates little heat to remove. 0 You are confused because the Vg voltage COMPARED TO "ground" (or the bottom, negative power supply rail) is zero, but compared to the source pin, it is actually negative few volts (Vgs = -x volts), and a P-channel MOSFET conducts or is turned on when the gate pin is a negative few volts (usually around -3V to -10V). The text mentions the gate "voltage" (the ... 0 The gate voltage is relative to the source. So when the Vgs is less than* the threshold voltage, significant current can flow from source to drain (often threshold is specified as something like 250uA). In your example where Vg is zero, Vgs is -Vin. So if, say, Vin is +5V then Vgs is -5V and the Rds (assuming a logic-level MOSFET) can be very low. * ... 1 The current through the base-emitter junction of a transistor is governed by the diode equation:$i_e = I_S \left(e^\frac{v_{be}}{n\ V_T} - 1\right)$. At room temperature,$V_T \simeq 26\mathrm{mV}$. So unless your peak-peak input voltage is significantly smaller than$26\mathrm{mV}$, you'll get distortion. On the bright side, you have lots of ... 0 First consider this simpler circuit:- simulate this circuit – Schematic created using CircuitLab If the op amp's inverting (-) input is lower than the non-inverting (+) input then its output voltage will go up, if the inverting input is higher the output voltage will go down, and when they are exactly equal the output voltage on R2 will equal Vi. ... 5 What would the operating region of both the transistors - Q1 and Q2? The Q1 is also working on the active region. Because for Q1 we have$V_B = V_C$hence the base-collector junction is not forward-biased. Because the saturation occurs when base-collector is forward-biased, for NPN we have$VB > VC$And if there's a load connected to the ... 3 GND is a term we can attach to any node on a circuit, usually it's a node with a lot of common connections and we usually refer to other voltages relative to that. It's not uncommon to have a node called GND that is not at earth potential, it may be floating, or (as in this case) it might be at mains potential. Suppose we have a Vdd for the MCU used in ... 0 Let's make the usual assumptions Op-amp inputs take no current. The output of an Op-amp will do what it can to try and make the inputs equal. This should give you the the current in$ R_2 $. Now the current in$ R_1 $is this minus the current in the base of$ T_3 $and the gain$ h_{fe} $is large. Note:$ h_{fe} = \beta = \dfrac{I_C}{I_B} $... 0 Assuming that the current flowing through R2 equals the current flowing through R1. V_{B,T1}=(V_{NI}-V_I)A V_{B,T3}=V_{B,T1}-V_{diode,T1} V_{E,T3}=V_{B,T3}-V_{diode,T3}=V_{I} Rearranging the equations yields: V_I = \frac{V_{NI}}{1+(\frac{V_{diode,T1}+V_{diode,T3}}{A})} For a considerable large gain V_I = \frac{V_{NI}}{1+(\frac{V_{... 1 The math comes from G/(1 + G * H) which is the easily revived transfer function [ math] for a certain type of feedback loop [ formal system concept == math]. 0 Ignoring the emitter diode drops, the output of opamp$V_o$is fully fedback to the negative input:$\begin{align}V_o&=(V_{+}-V_{-})A\\&=(V_i - V_o)A\\\Rightarrow V_o &= \frac{V_iA}{1+A}\\&\approx V_i\end{align}$0 The OpAmp is trying to bring the potential difference between both inputs to zero. So assume the OP is regulating the output to such a voltage level, that the negative input has$V_i$as well. Because the negative input is directly connected with the node between T3 and R2 the voltage at this pooint is also$V_i$. The current through R2 is now given by$...

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I have checked some info on the ESP8266-01, and your problem is that BOTH the GPIO and GPIO2 need to be pulled UP for the chip to start working. The GPIO2 in your case is pulled DOWN through the base of the transistor. The chip at startup checks the GPIO pins, and then it makes them available for use as inputs and outputs. That's why your chip works without ...

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One problem that I can see with your circuit is that the 2N2222 transistor may not have sufficient current gain to turn the relay on (and keep it on). The relay may need anywhere from 60 to 100mA, the transistor gain is guaranteed around 50 at around 100mA AND (this is VERY important) 1.0V across the collector-emitter junction. This means that you might ...

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That resistor speeds up turnoff and increases maximum allowed collector circuit voltage. The turnoff speeding is based on the fact that the charge which is stored to the BE junction is dissipated in resistor R2. The effect is substantial in pulse circuits. There's some leakage from C to B and it can cause substantial unwanted base current at high operating ...

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