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1

You just need to download older drivers for Usb to TTL prolific and it works. Had the same issue, i just downgraded from 3.8 to 3.0 drivers. Check the device manager on your windows under Ports if you see a yellow warning icon next to your device it is because of drivers. (This works for cloned PL2303, original works with new drivers)


0

If you want the "master" to be able to override the "slave", you need to put the resistor in series with the slave's transmit pin: simulate this circuit – Schematic created using CircuitLab But what you're doing on the "B" side of the '245 is completely invalid. You can't just tie four of the pins together like that. For receiving, a 4-input AND ...


1

Your observations are all correct on the measurement differences between the 74LS TTL series “Gate” and “Buffer”, including the discrepancy in one line of the Wiki page which led to your good question. It should have said digital buffers can drive more **current than their “standard” equivalents. In TTL this is done by design using resistor values to define ...


4

Yes, the ‘LS37 is a buffer. The high drive figure is used for driving higher fan-out loads. Some other logic gates have equivalent high-drive ‘buffer’ versions. There are also some that are open-collector so that they can be used for wired-or buses and logic. There are still others designed to drive transmission lines. At any rate, higher current is ...


0

It's also worth noting that when I generate a square wave, it overlaps with the trigger pulse exactly. This may be a clue. It would be logical to use the same squarewave signal for both. The better question might be, "How is the sinewave generated from the square?" If this is done by look-up table, for example, then the trigger point could be any point on ...


2

The TTL gate is in either of two states. If its emitter is high (all of them), Q1 is cut off. Current flows through its B-C junction and turns on Q2, driving the output low. If any of Q1's emitters is pulled low, then it conducts, pulling the base of Q2 low. There is a small transient current when this occurs, but no DC current. Since the base of Q2 is ...


1

3.3V LVTTL logic only guarantees a high of 2.4V (Voh) at its rated current. What is the load? If it’s too much for your device you may need to add a buffer. If it needs to be a ‘true’ 3.3V, then it needs to be a FET buffer which can swing all the way to the positive rail.


3

The delay you require is only 25nS. I would consider simplifying your circuit to use two or all three of the other gates in the 74HC86 package to provide the delay, their nominal Tpd is 11nS at 5v into 15pF. Without extra capacitive loading, their delay might be a bit less. Their delay will be strongly affected by the rail voltage, so only use this method if ...


8

However looking through the datasheets I found that MAX9010 outputs TTL levels, while 74VHC86 accepts CMOS levels (0.7 * Vcc). That's a good spot and I agree with you - maybe you should inform Maxim on their dodgy circuit. Shame on them. Should I pay special attention to this issue - what are the conditions when circuit may fail producing proper ...


2

UART communication uses positive logic. In TTL, logic 1 is 5V, logic 0 is 0V. However, in UART, the idle, no data state is 1/HIGH, not 0/LOW. What you are seeing here is not inverted logic level, but simply an idle UART line. The Wikipedia article on Universal asynchronous receiver-transmitter has a good explanation. Data framing: The idle, no data state ...


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