54
Check that the GPIO pin for UART TX is configured for alternative output push pull mode. It looks like it is configured for alternative output open drain.
9
Synchronous communication will have a clock line and a data line. That makes it very easy:
The TX sets the data on the data line and then strobes the clock line.
The RX waits for the clock strobe and then reads the data.
It doesn't matter what the baud rate is and it could even vary during the transmission of a byte, for example.
In Asynchronous data ...
7
Do you have a schematic for your circuit?
In addition to the misconfigured GPIO pin, another possibility is that you have a capacitor on your UART line, acting as a low-pass filter, and preventing the signal from rising quickly.
6
1 MHz clock cannot achieve 9600 BPS rate with 16x oversampling. You must use faster clock, slower baud rate, or use U2X bit to enable 8x oversampling.
6
In a typical situation between two communicating systems A and B there are two signals:
One from A's transmitting output to B's receiving input
One from B's transmitting output to A's receiving input
Same speed in different directions?
Other than simplicity, there's no particular reason the signal should go at the same rate in the two directions. Many ...
5
Most likely the malloc and free are not thread safe so you can't allocate in interrupt and free in main loop. In general, there should be no dynamic memory allocation in interrupts. At least you should disable receive interrupts when popping a byte from the linked list. And in general rarely there should be need for linked lists using dynamic allocation in ...
5
"Synchronous" means (in this context) that there's a separate line that just carries a clock strobe that tells you "when this signal goes high, measure the voltage on your RX line to get a value".
In asynchronous communications, there's no such signal. Instead, the receiver just watches the RX signal for a beginning-of-frame marker, and then simply measures ...
3
CSCTL1 |= (DCORSEL | DCOFSEL_3);//DCO 8Mhz 0x0046
The comment is wrong. This sets the FSEL field to 7, which is invalid and results in 24 MHz, which does not work without more FRAM wait states.
If you do not want to keep any bits that happen to be set in the register, do not use the | operator.
And you should clear the password after you have initialized ...
3
As mentioned above, setting it to output push-pull mode will solve the problem, however you may also want to check the "Maximum output speed" is set to 'very high', and if your system tolerates it, add the internal pull-up resistors; I know there's various schools of thought on whether USART should have pullups or not, so try it and see if it does what you ...
3
There are 7+ mainstream STM32F0 MCUs with 8 USART interfaces. There are several high performance STM32F4/F7 chips with 4 USART + 6 UART (for 10 total) interfaces, and three dozen chips with 4 USART + 4 UART (for 8 total).
I am pretty sure you can find similar options from other manufacturers if you stop looking for DIP package. The adapters from LQFP to DIP ...
3
Yes, it will misinterpret things.
2
UART is very robust when it comes to clock accuracy requirements. This is a consequence of the fact that each byte is processed independently and any time difference associated to clock mismatch doesn't propagate for more than 10 bits (start bit + 8 data bits + stop bit) in time.
This analysis from Maxim concludes that 2% in clock frequency mismatch is ...
2
What are you connecting your UART/serial comms to?
The MAX3323 uses external capacitors to generate +5V and -5V, and uses those supplies to convert signals from the low-voltage side into signals which transition between +5V and -5V. It only requires one low-voltage supply to do this.
The shield devices you link to require an external supply ( +5V ) to be ...
1
yes, for such slow signals either kind would work.
Or you could use resistors for voltage drop and a TTL compatible buffer for the upwards shift.
but "rock7" says
There are various FTDI USB cables, the precise model used with our products is the TTL-232R-3V3, and it's available to purchase from our shop or from various electronics outlets ...
1
The Teensy will be fine with 5 V on the inputs; that's what tolerant means. The main question is whether the 3.3 V output from the Teensy will be recognised as a logic HIGH by the RockBLOCK. The answer is in the datasheet:
T/Rx High Minimum: 3.0 V
As long as the Teensy will drive the load to a voltage >3.0 V, it will be fine.
However, given the cost of ...
1
Especially if you have a crystal-controlled UART at the other end, you are reasonably safe with as much as +/-5% error.
However that error should include initial oscillator error, drift error (temperature, Vcc, time etc.) and any error in divider digital ratio.
1
No, because the UART stands for "asynchronous". You have somwhere in the datasheet a ratio baudrate vs sampling clock, so it is oversampled, then filtered (decimated). The asynchronous clock is reset once the start bit is detected, so there is plenty room for clock inequalities.
For the standard oversampling ratio of 16 , the clocks can be off by +/-5.11% (...
1
If you turn the receiver on after the start of a data word, then of course, the receiver will not interpret it correctly. You could regard this as misusing, rather than using a link.
If the word is immediately followed by a further word, then the misalignment can continue. As long as bit 2 is 1 and bit 3 is zero, the RX will 'see' a start edge at the time ...
1
Usually in the PLC communication world terms cyclic means data that are exchanged each scan continuously, for example IO variables, meanwhile acyclic means you send something on demand also you receive the response, usually this means the exchange of parameter data, configuration, diagnosis,..etc.
What are you looking on particular page of linked spec. is ...
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