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Was an ASIC Design Verification Engineer at Qualcomm. In the most simple way I can explain it: Testing: Making sure a product works, after you've created the product (think QA). Verification: Making sure a product works BEFORE you've created it. They're both testing, just that verification is more complicated because you have to figure out a way to test ...

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I can only answer this question from my point of view, so I am doing so to start the conversation, not because I expect this to be an exemplary response! EDIT: there is a VERY good ESE answer here that I think would be of interest to anyone reading this. Let me start by saying that I am based in the UK, and work for a small, young company (I hate the word ...

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All chips, from the very simple to insanely complex, have functional specifications. These describe what the chip does. The IC designer will make a circuit to implement that functional spec, while a validation engineer or test engineer will develop a set of tests to check the implemented chip against the same functional spec. It's not necessary for a test ...

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Electromagnetic Interference is a radiated or conducted signal that is unwanted that you are trying to avoid. Electromagnetic Compatibility encompasses the standards and testing of equipment so that it can generally be expected to function properly in a shared environment. This involves testing devices to make sure that the EMI produced is under some limit, ...

7

The answer to the question depends on where in the world you are located. Let us for discussion's sake assume Europe. The rest of the world seems to be accepting or even adapting to the European bureaucracy model, so it applies somewhat globally. It goes like this: The European Union has invented a system where the responsibility to know about every ...

6

In my book Verification is ensuring that what you have designed "does the job" - i.e., you have a set of things the "device" needs to perform, and verification ticks those off on the list. Testing, though, is making sure that the things the "device" does are done right. You have a set of functions, and you test each function making sure that function ...

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I can answer this for my particular experience in ECE. Digital design, embedded design, and system design. Essentially we do all the same tests as software folks. Design reviews We have manual reviews of designs for digital implementations, PCBs, and analog circuits. Similar to code reviews. For embedded designs, the embedded code is reviewed similarly to ...

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UL listing is most common in consumer goods, and appliances in particular. The reality is the consumer doesn't really care whether or not a product is listed. The people that care are the retailers and insurance companies. Consider a Wun Hung Lo toaster with so many corners cut in design and manufacture, it's a circle. Walmart buys a shipping container at $... 5 SystemVerilog included a range of new features intended to improve verification productivity and the most significant are probably: Object Oriented programming Constrained randomsation Functional verification in simulation is entirely a software problem, so by including classes the verification community acquired all of the productivity gains of ... 4 There is nothing wrong in using open source software or hardware to design medical devices. But at end of the day provider of these equipment has to comply with regulation in jurisdiction the devices are sold. I have experiences ubuntu (Linux) computers used in US doctors offices. In general in USA and Europe the devices have to be compliant to government ... 4 Coming from a an ASIC (hardware) design background, there are three important terms: validation, verification, and test. The earlier answers generally talk about one or two of these terms, but don't clearly contrast all three in the way I would. Here's the way I understand them: Validation: does the specification (often a C model) meet market or customer ... 4 From someone actually having done some serious work on the certification business of a medical device. Others already wrote at great length so I'll just add some other points. 1st, you cannot know what you need to fulfill unless you have someone to advise you. I suspect you're trying to get some free advice here without paying consulting fees... For tightly ... 4 Verification is a huge part of the design process; in a complex design, it would not be unusual to spend as much time, or even more time on verification than you do on the actual design. That being the case, a question which is essentially 'how do you verify complex designs' is quite broad. In overview, if the design copes with a large number of scenarios, ... 3 This is a very broad topic. I hope you will receive more than one response. My response is based on my experience in the automotive space. The test and validation for consumer and medical space is fairly different. As I understand the Aerospace is much different. Depending on the product automotive space primarily has to validation phases which is Design ... 3 Basically a specification is a list of requirements. A requirement is generally defined as any statement that has the word "shall" in it. For example, a specification for a digital multimeter might include the following requirement: " The DMM shall have a display resolution of 3000 counts". A function is a capability of the equipment. Again, using A DMM as ... 3 By definition, a sequential circuit has "state" (memory), and its outputs are a function of both its inputs and its internal state. This can only be done if it contains one or more internal feedback paths. Usually this feedback is embodied in the form of flip-flops and latches, but there are other kinds of feedback that can be used to create sequential ... 3 Formal verification is state-point mapping done to ensure a schematic matches verilog or RTL model of the module. This means that for every set of inputs and states defined in the RTL model, the design is checked against the schematic to ensure that for those same inputs and states, the outputs are the same. It is a bit more cumbersome than other ... 3 Why such a huge range? When I built my smart cat door 40 years ago I used RF. I used a 10nF polyester capacitor, and wound a few turns of wire around it, and potted it in resin, including a small hook to attach to the cat collar to make a dongle for the cat. Then built an oscillator at its resonant frequency. I built a flat search 'coil' using veroboard (... 3 Yes, you can certainly use FPGAs to do this kind of work, there’s lots of literature pointing to it. Examples - [1] [2] [3] [4] SMT = Satisfiable Modulo Theory SAT is Boolean Satisfiable Problem, nicknamed a ‘SAT’ for short. More about this stuff here: https://people.eecs.berkeley.edu/~sseshia/pubdir/SMT-BookChapter.pdf My suggestion is to address the ... 2 Based on the error message, you are not including the UVM source in your compile. Some tools have UVM built-in that can be enabled with the -uvm argument at compile time (refer to the user manual). Alternatively you can add +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv as a compile time argument, where$UVM_HOME is the path to the UVM source. This method works ...

2

Code coverage is a metric that tells you if you have executed each line of code in the implementation of your design. There are a number of other metrics for code coverage that tools can easily calculate for you non-intrusively (e.g has each single toggled to their true and false states). The theory is that you could not have tested code that was never ...

2

Code coverage means that you have verified all of the lines of code in the design. For example, if there is an if statement, you have checked both branches. Functional coverage is where you have verified all of the scenarios that the design is to be used. These scenarios are generally from a user or a system point of view. Just to give another point of ...

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A very large part of the meaning of the certification comes from the full name. UL is short for "Underwriter's Laboratory." Back when UL was founded, Underwriter was a term for insurance companies. The labs were founded to give the insurance companies a way to check materials and devices before agreeing to insure a company that used or produced the ...

2

EMC testing generally refers to both emissions and immunity testing. However some engineers refer to immunity testing as EMC testing and emissions testing as EMI testing. Electromagnetic interference (EMI) generated by electronic products can be an issue both internally and externally to the product. Regulatory agencies such as the FCC put limits on the ...

2

This question is more legal than engineering one, and I'm not a lawyer. However, my understanding is that a medical device is a function, not a technological capability. If the device is used to diagnose or threat actual patients, it is a medical device and has to be certified as such. If you built a toy brain wave monitor, no certification is required. You ...

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A general approach is to use more abstracted tests as you progress up the stack in terms of design complexity. Yes, you need to trust the tools (and the checking tools like logical equivalence proofs), but for a whole-fpga design (a) there won't be space for a testbench, and (b) exhaustive coverage will take a long time. A good approach is to use exhaustive ...

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Can you check if a file is the same over time and location? Yes. It's called check-sum. Can you use the instruction format in the files to check? If the format is deterministic, of course you can. Just generate the instructions again and check if they are the same. Do you want to make your own tools for that? Sure as hell hope not. MD5 is a file-to-file ...

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Verification is a huge field. Just like in software there are many levels of verification e.g. code coverage, path coverage etc. It all depends on the application. Blinking LED: check the frequency in simulation; the control system that keeps your turbofan below its melting point: you better test the hell out of it. We can split verification into two main ...

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The code you wrote should work. The only possible problem is that you should use $realtime instead of$time if the current timescale is greater than 1ms. That prevents time from being rounded to an integer. I can rearrange the begin/end blocks to better explain how it executes. always begin @(negedge sig) // wait for sig to goto 0 sig_low =...

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Asking for a bin for "everything else" to be counted towards coverage is the same thing as not specifying any bins for your coverpoint. If you are trying to get a particular set of bin groupings, you might be better off specifying two coverpoints of the same expression. The first coverpoint has the bins you specifically wanted to pick out, and the second ...

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