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4 votes
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Result is XXXXXXXXXXXX for Verilog

You need to toggle the clock signal in the testbench. Currently, clk is always 0. Add this to the testbench module after the ...
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3 votes
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Why does adding "& 1" to an assign statement produce a completely different synthesis?

The unique thing about Verilog compared to other programming languages is the concept of operand width and the context of operands and operators with different widths. The widths of certain operands ...
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2 votes
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SystemVerilog testbench giving don't care (X)

The problem with reading the signaldata.txt file is that you are using the wrong tool for the job. You should use $readmemb ...
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1 vote
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Multiplication 32x32 Mealy machine using 16x8 multiplier Verilog code

To debug Verilog simulations, you need to look at waveforms of internal signals. When I look at your FSM, I notice current_state never changes (it remains in its ...
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1 vote
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Syntax error in continuous assignment

Some simulators do not yield very descriptive error messages. But, others sometimes do. You can try to compile your code on multiple simulators available on the ...
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1 vote

Why is order of bits not getting reversed?

The order looks the same due to how the waveform viewer displays the 2 signals. For in, in[0] is the rightmost value in the ...
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