3
votes
Accepted
Registers Not Updating in 16-bit RISC Processor Verilog Implementation
The Verilog simulation does not behave as you expect because you are not following good Verilog coding practices. Specifically, you should not make multiple nonblocking assignments to the same signal....
- 9,763
1
vote
Accepted
Register initial value without explicit reset input (Verilog)
It depends. If you want portability with every possible synthesis tool on the planet, then yes, you still need to use an explicit reset. But realize explicit resets take up extra area and power. If ...
- 8,935
1
vote
Accepted
What happens in Verilog when I assign the value of a button to a register with a non blocking assignment?
"value" is scheduled to be 1 at the end of the current clock cycle
That is incorrect. You misunderstood the meaning of nonblocking assignments. value ...
- 9,763
1
vote
Memory module with SR-Latch - value overritten when writing to another cell
The fundamental problem is that you have been lead down the wrong path with your approach to Verilog modeling. You should always write Verilog code at the highest level of abstraction. You are ...
- 9,763
1
vote
Accepted
Verilog - problem reading giving wrong value at interconnected bus
the write operations work successfully
There is insufficient evidence of that in your question. Instead of relying solely on the information in your simulation log file, you should also dump ...
- 9,763
1
vote
Accepted
Verilog - 8x8 memory unit - wrong value read
Any ideas?
Yes, there are plenty of ideas.
Since your simulation log indicates there are problems with outp, you need to focus your debug efforts there.
Just by ...
- 9,763
Only top scored, non community-wiki answers of a minimum length are eligible