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10

This code is effectively creating an inverter with its input connected to its output. If the propagation delay through the inverter is long enough you will get a "ring oscillator". The frequency of oscillation is determined by the delay through the inverter. So, if you have a free-running oscillator what will be the value of its output at any given ...


8

As others mentioned/explained, undefined behavior is not the same as 'randomness'. And I believe you misunderstood the meaning of always @(*) construct in your example code. Simulator perspective First of all, it doesn't mean that randomly flip the value of tempBit. It means that: 'Simulator may trigger this always block for any changes in the values (i.e., ...


6

Can always @ (*) introduce randomness in FPGA? It's undefined behaviour. That can be random, but it's more likely to be a constant value, that might even be chosen during synthesis to optimize this structure away. "Undefined behaviour" means your synthesize can do with this what it wants, since it literally can't make things any worse. Setting the ...


2

Your code doesn't follow the general coding guidelines, for example: You are using blocking assignments for registers inside the clocked always @(posedge ..) block. It has to be non-blocking assignment like for eg: counter <= 32'b0 ; You have a combinational loop in the combinational always @(*) block, which has undefined behaviour. Shouldn't you use a ...


2

the sequence diagram always starts with many '0' outputs. It is because, the Multiplier block you use is a pipelined design to increase the throughput. Every pipelined design has an initial latency, after which you get the outputs every clock cycle. The latency is what you have configured during the instantiation: .LATENCY(3), As you can see the ...


2

You can't keep both the indices of the range a variable, while indexing an array in Verilog. At least one index has to be a constant for the Synthesiser to be able to resolve the expression. Verilog has a standard syntax to address your intention: acc [count +: 3] This is called part-selecting, where 3 signifies no. of bits of acc being addressed, and the ...


1

The generate loop would go outside of the always, but there is no need to complicate your code with a generate. The for loop on its own is sufficient: module CrossBar( clkIn, inputs, switches, outputs); parameter NUM_IO = 4; parameter NUM_SWITCH_BITS = 2; input ...


1

There is no way to do this in synthesizable SystemVerilog. I assume you tagged this fpga to be synthesized into an FPGA, otherwise I would have recommended using classes instead. The closest thing you can to do is create two different struct types and pass on of them as a type parameter to a module. But when you pass the CFG_A struct into the module, that ...


1

Well, the error messages are very clear: You're driving the same output signal with multiple drivers. And that's exactly what your code (and schematic) show: you're driving out2 with several ring oscillators. Obviously, that's not "proper" digital design, so the synthesizer stops you from doing that. It's not clear what your intention there is – it ...


1

If you only need a small buffer (<16 data entries), there's absolutely no reason to prefer BRAM over LUTRAM. BRAMs are located in specific areas of the chip, which may mean that relatively long paths are required to get to them from your other logic. LUTRAM can always be located close to the logic that uses it. On the other hand, larger buffers (>64 ...


1

What you've encountered there are the problems that come with instruction pipelining. I assume that you're going to synthesize your processor for running it on an FPGA at some point, so removing the register between the instruction memory and the rest of the CPU is sadly not an option. To fix this, you have three options. Ignore the problem. After all, your ...


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