# Tag Info

7

*| is not a single operator, but the combination of two different ones. Unary reduction OR |, followed by a multiplication *. The code: CONVERTERS+(LANES-CONVERTERS%LANES)*|(CONVERTERS%LANES) is equivalent to: CONVERTERS + ( LANES - ( CONVERTERS % LANES )) * ( |( CONVERTERS % LANES )) Basically if CONVERTERS is a multiple of LANES (modulo remainder is 0), ...

4

As long as you write to a variable with a blocking assignment before you read it within the same always block, and you do not try to read outside that block, it's considered a temporary variable and gets synthesized into combinational logic. Once you try to read it outside the block, it becomes sequential logic and you run the risk of a simulation race ...

3

There are two key rules with assignments in clocked always blocks. Do not mix blocking and non-blocking assignments to the same reg. Doing so is likely to cause a synthesis failure. Do not read the result of a blocking assignment from outside the always block where it was set. Doing so can make the behavior of the code unpredictable, because the order in ...

3

Vivado synthesizes RTL into Xilinx primitives (LUTs), not gates. If your objective is to target a standard cell library restricted to gates and flops you need a synthesis flow (like Synopsys DC /VCS) that does that.

2

Three sinc filters in series is a third-order sinc = $sinc^3$) and ... six sinc filters in series = $sinc^6$ or two $sinc^3$ filters in series. More info ( re-search) https://www.wikiwand.com/en/Sinc_filter Definition of SINC in t or f domains https://www.ti.com/lit/an/sbaa230/sbaa230.pdf Digital Filter Types in Delta-Sigma ADC https://www.mouser....

2

Taking a step back, the simplest solution to implementing ROM (a) using Block RAM, not LUTs, and (b) allowing switching between different compilers and target FPGAs is to use a component. Define your ROM as a separate Verilog entity/component (using VHDL terms), say MYROM. Then produce two MYROM design files: one for use in Altera Quartus, one for Xilinx ISE....

2

If you want to use the ternary (conditional) operator, you can use case equality (===) instead of logical equality (==): i0_reg <= (i0_reg === 0 ? (1'bz) : 0); Refer to IEEE Std 1800-2017, section 11.4.5 Equality operators. The behavior you observed is not a bug and it is not specific to iverilog; it is observed on other simulators as well. In your ...

2

Yes, this is perfectly valid as long as you want both your "t" and "tt" outputs to be synchronous. (Also note that you wrote "d" instead of "t", I assume that's a typo.)

1

If you perform the division manually in binary (long division), you will see that it can be done by a regular array of combinational logic in a way that is a little more complex than addition-with-carry. I have done this previously, just don't have the code available now.

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