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2

The problem is with your combination of the write address and the write strobes. Your write addresses are 1,2,3. But at the same time your write strobes are 0xFFFF thus all 16 byte lines are active. That is not allowed with the addresses of 1,2,3. The first 1, 2 and 3 byte strobes must be zero because you address is skipping those bytes. See figure A3-13 ...


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Your count starts at X (actually it starts 4'bxxxx.). Now if you add 1'b1 to 4'bxxxx you still have 4'bxxxx. Sort of like a dead-lock The only way to break this deadlock in your code is to apply a reset whilst the clock is running. That forces the counter to zero and after removing the reset you can use it to count.


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Thats a wrong conclusion you are leading to , whenever you have designed the verilog/vhdl module in the constraints file you need to provide the following information, Physical constraints -- Pin location constraints, IO Standard of IO pin(you can see the VCCO,VCC_AUX values in case of xilinx fpga similarly you can see for other FPGAs too),Slew ...


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Your question is rather broad. To start with: the good new is that you don't need to buy an FPGA board to find out how big your design is. The development tool will tell you. It will also tell you if you exceed the number of resources (Memories, LUTs, Registers, DSPs or I/O pins.) If it does not fit, you select a bigger FPGA in the tool setting, until you ...


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Then write it into output c in the next clock. No you don't. e[i] does not receive that value until the next clock cycle. Thus c <= e[i]; gets the old value of e[..]. But by the next clock cycle you have changed i, you incremented it: i <= i + 1; so c still does not get that value of e[i]


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In SystemVerilog, wire and tri are aliases for identical net types. Section 6.6.1 Wire and tri nets in the IEEE 1800-2017 LRM explains that the driver with the strongest strength will use its value for resolution. There's no way for a net to have different values when connected through a port, but I assume you meant the driving value in each module. So the ...


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The larger and more timing-critical your design, the more it should be aware of the underlying logic resources implementing it. This is true whether you’re working with an FPGA or ASIC flow. You will need to understand this to get the device to fit and to close timing. FPGAs have hardware macros that help with this: RAM, special I/O, ALU/DSP blocks, ...


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You din is changing at the same time as the clock edge. This is a race condition and as such the behavior of the simulator is not defined. This is because you use blocking assignment here: always@(posedge clk) begin if(rst_n) begin din = 4'd15; // << WRONG! end end Change that to a non-blocking assignment: always@(posedge clk) begin ...


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I solved it, I actually answered this with my question above. I doubt that there will be another noobie like me having such a basic question but here it goes. Once you declare a constraint name and implement it in a module. It seems that this constraint can not be renamed and passed from another module. It has to have the same name. Example some pin named ...


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It's reporting the error a few cycles later. But that is the problem--at the point BVALID is asserted, AWREADY is still 0 so the write handshake isn't complete.


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Just connect your signal to the clock input and use an async reset: module see_shorty ( input short_signal, input short_signal_clear, output reg short_signal_seen ); // You can make this negedge short_signal to detect a falling edge // In the same way you can invert the reset signal always @(posedge short_signal or posedge ...


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How bout something like this? The clock is your local clock, common to all the flip flops. R is the reset (usually power on) for the FFs. The glitch filter is optional. Answer to OP's Question S is just the SET input of the flip flop.


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Static Formal tools are great at this. They have the ability to trace paths and validate assertions you make about them. There is a special segment of formal tools called connectivity checkers just for checking proper interconnect of the blocks that make up your SoC designs.


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I have modified your Test Bench and Design code, now u wont encounter the crash issue but i definitely think there is an issue in your stimulus in Test Bench. `timescale 1ns / 1ns module moore_fsm_tb; reg clk; reg rst; reg inp1; reg inp2; wire oup1; wire [1:0] cstat; wire [1:0] nstat; localparam TIME_PERIOD = 2; localparam INP_X = ...


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You could possibly change the logic so that you generate an interrupt pulse more than 1 clock cycle wide. Start when you wrap around but continue until the count is 2 or 3 maybe? Will an interrupt that is a few clock cycles wide cause your CPU to process it as multiple interrupts?


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This type of thing is normal within the synchronous system. It is like you have one DFF after another - the signal will propagate to second DFF only when first has changed its state on previous clock edge. Think about changing clock edge your interrupt line is activated with - you can use negative edge of the clock, and then next time posedge happens, just ...


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