13
votes
Accepted
What is the meaning of "e" in this timing diagram?
e is a numeric value displayed in hexadecimal format. It is the same as 14 in decimal. It means that bits in[3:1] are set to 1,...
- 6,980
6
votes
Accepted
Why I am getting one clock cycle delay in Verilog case statement?
At the positive edge of clk you change from WAIT state to SERVE state. You don't change the ...
- 64.8k
5
votes
What is the meaning of "e" in this timing diagram?
toolic is correct; this is simply 0x0000000E.
The important part of the description is the following:
The output bit should be set (to 1) the cycle after an 1 to 0 ...
- 3,411
4
votes
Why I am getting one clock cycle delay in Verilog case statement?
The other answer directly answers your question about the relative timing of your output signals, and it also provides an astute observation of a probable bug in your code (...
- 6,980
2
votes
Accepted
How to select a handshake and code examples in verilog
Ready-valid is very good in a synchronous design, because it allows high bandwidth (transfer on every clock cycle) and precise flow control. That's why it's used in the AXI interface, which is the ...
- 171k
1
vote
Does SystemVerilog have (others=>'0') expression like VHDL?
Yes, SystemVerilog supports:
data = '0;
data = '1;
data[7:4] = '0;
data[7:4] = '1;
Refer to IEEE Std 1800-2017, section 5.7.1 Integer literal constants:
An ...
- 6,980
1
vote
Verilog counter delay in task not working
Since you are new to Verilog, here is a quick start to learn about synthesizable constructs. It is not common to use a task for synthesizable code; they are much ...
- 6,980
1
vote
I2C slave PWM Verilog problems
The problem is in the testbench code. You did not drive the SCL input. Change:
.SCL(SCL),
to:
...
- 6,980
1
vote
How do I set a 4-channel PWM with I2C in Verilog?
When I compile your Verilog code with the Synopsys VCS simulator, I get a warning message:
...
- 6,980
1
vote
Verilog error: cannot be driven by primitives or continuous assignment
You must not declare temp or Product as reg type. Simply remove the ...
- 6,980
1
vote
Verilog error: cannot be driven by primitives or continuous assignment
The key part is:
reg cannot be driven by ... continuous assignment.
Variables declared as type reg can only be assigned in ...
- 64.8k
1
vote
Why am I getting unknown states in output for Booth multiplier Verilog code?
When I run your simulation and trace the unknown outputs back to their sources, I see that the controller module has several signals which are unknown: ...
- 6,980
1
vote
Accepted
Under which situation must a signal be defined as a reg?
Under the old version of Verilog (IEEE Std 1364), continuous assignments using the assign keyword would typically be to signals declared as ...
- 6,980
1
vote
Defining vector in Verilog
Until you specify a direction, a parameter "inherits" its size and direction from the previous one.
Re-write the module definition:
...
- 30.5k
1
vote
Accepted
Defining vector in Verilog
The format is:
<direction> <type> [<packed size] list,of,var,names
The same principle applies to all variables.
So in your example as ...
- 64.8k
1
vote
Why does it take so much time for compiling verilog HDL code in Quartus?
By assigning a constant to the output, you're making all of the other code in the module unused. The logic optimizer in Quartus will of course remove all of the unused logic, leaving you with what is ...
- 15.6k
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