Podcast #128: We chat with Kent C Dodds about why he loves React and discuss what life was like in the dark days before Git. Listen now.

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An X means a register is not initialized. You have NOT provided the code for the registers or register banks. Thus the code most likely to cause your problem is missing. However some of the code you did provide is wrong. This does not work: always @(posedge reset ) begin if ( reset ) PC_reset <= 0; end assign PC = PC_reset; register_32_bit ...


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Your "Write to a register" is not using a clock: // Write to a register always @(*) begin if (Reset) RegInputMatrix[WriteAddr] <= 16'b0; else RegInputMatrix[WriteAddr] <= WriteData; end Thus it becomes a latch. Also that code look suspicious in the reset section. On a reset you only want to clear the register with ...


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To chain smaller adders to make larger ones, you need the building-block adders to have carry in and carry out connections and you need to link those connections from one ader to the next. Your diagram does not match your code, your diagram shows a carry connection, but your code does not. You need to expand your add16 module to support carry in and out ...


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Declare the intermediate wires between the stages inside the generate loops wire Ain[0:15]; genvar Cv,Bv,Av; wire Din[0:1]; mux2 Dm( Y,D ,Din[0], Din[1]); for (Cv=0;Cv<2;Cv=Cv+1) begin : Clevel wire Cin[0:1]; mux2 Cm( Din[Cv], C, Cin[0], Cin[1]); for (Bv=0;Bv<2;Bv=Bv+1) begin : Blevel wire Bin[0:1]; mux2 Bm( Cin[Bv], B, Bin[0], ...


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Seems like your file path is causing problem. Specify full file path to .mif file Anyway Vivado will synthesise only a distributed RAM for your array music. To use Block RAM, you have to generate one with initial values in a .coe file and instantiate it. But then, you can access the data only one at time in a clock cycle. You can't access multiple data in '...


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