5
votes
Accepted
Strange thing with concatenation and adding in Verilog
The result from a concatenation operation is always unsigned, even if all its operands are signed. Also, a select of a signed value is unsigned even if selecting all the bits. That means your addition ...
- 6,229
4
votes
Accepted
How to run assembly code on Verilog CPU design?
This project gives you several choices.
The project provides python scripts to convert assembly language to a hex file, and an interpreter/emulator that reads the hex file and executes it.
You can ...
- 6,229
4
votes
Accepted
Why is my output showing X despite all inputs driven in my simulation?
You get X (unknown) because the Errors signal in the testbench has multiple drivers. It is driven both by the wire assignment ...
- 2,856
4
votes
Accepted
Verilog mux select condition not correctly evaluated
Table 11-2—Operator precedence and associativity in the IEEE 1800-2017 SystemVerilog LRM defines the order of operator precedence. From that table, the order of your operators is
+ (binary)
== (...
- 6,229
3
votes
Reading a file in Verilog
To read integer values (positive and negative) in decimal format, you can use the $fscanf system function. Refer to IEEE Std 1800-2017, section 21.3 File input/...
- 2,856
2
votes
Accepted
Problem with reading a .csv file into a Verilog module
Try inserting commas ,
j = $fscanf(f,"%b,%b,%b",r1,r2,r3);
- 6,229
2
votes
What does the "#" in this Verilog module instantiation mean?
Well, after some searching, I found a possible explanation:
When we want to instantiate a Verilog module with parameter, like this:
...
- 21
2
votes
What is the maximum limit of signals in sensitivity list of always block?
The Verilog language itself does not have a limit, but software and hardware does have limits; even with always @*. Over 10 years ago I worked on an unusual BFM ...
- 4,110
1
vote
Accepted
1
vote
How to run assembly code on Verilog CPU design?
The CPU in your link is a soft CPU, from an FPGA/CPLD perspective. The Verilog HDL source files carry the digital logic circuit design for the CPU.
The CPU is just one part of a microprocessor, which ...
- 18.6k
1
vote
Accepted
Testing an array of instances using an input file
The problem is that you are driving the same 4-bit input value to each instance of your Lat module inside the Lat_array module.
...
- 2,856
1
vote
Accepted
Parameter binding error in Icarus Verilog
You have an if construct outside a procedural block (initial or always) That makes it a non-...
- 6,229
1
vote
Accepted
Verilog port width larger than defined
A parameter value can be overridden when a module is instanced inside another module.
Since in1 is 224 bits wide, and since 224 =...
- 2,856
1
vote
Do wire/net type constructs in Verilog map to programmable interconnects/ switching matrix of FPGA?
well, of course the HDL code gets converted into connected logic, not only logic: What good would unconnected LUTs do? They'd not be representing the HDL functionality.
So, yeah. That routing is part ...
- 79.1k
1
vote
Verilog help: .V to schematic
Verilog doesn't describe a circuit of logic gate as you want it. That's one possible mapping of a subset of Verilog functionality.
But in general, verilog literally just describes the netlist as a ...
- 79.1k
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