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Strange thing with concatenation and adding in Verilog

The result from a concatenation operation is always unsigned, even if all its operands are signed. Also, a select of a signed value is unsigned even if selecting all the bits. That means your addition ...
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4 votes
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How to run assembly code on Verilog CPU design?

This project gives you several choices. The project provides python scripts to convert assembly language to a hex file, and an interpreter/emulator that reads the hex file and executes it. You can ...
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4 votes
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Why is my output showing X despite all inputs driven in my simulation?

You get X (unknown) because the Errors signal in the testbench has multiple drivers. It is driven both by the wire assignment ...
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4 votes
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Verilog mux select condition not correctly evaluated

Table 11-2—Operator precedence and associativity in the IEEE 1800-2017 SystemVerilog LRM defines the order of operator precedence. From that table, the order of your operators is + (binary) == (...
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3 votes

Reading a file in Verilog

To read integer values (positive and negative) in decimal format, you can use the $fscanf system function. Refer to IEEE Std 1800-2017, section 21.3 File input/...
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2 votes
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Problem with reading a .csv file into a Verilog module

Try inserting commas , j = $fscanf(f,"%b,%b,%b",r1,r2,r3);
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2 votes

What does the "#" in this Verilog module instantiation mean?

Well, after some searching, I found a possible explanation: When we want to instantiate a Verilog module with parameter, like this: ...
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2 votes

What is the maximum limit of signals in sensitivity list of always block?

The Verilog language itself does not have a limit, but software and hardware does have limits; even with always @*. Over 10 years ago I worked on an unusual BFM ...
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1 vote
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Why is my output showing as X?

The simulator I am using generates compile warnings like: ...
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1 vote

How to run assembly code on Verilog CPU design?

The CPU in your link is a soft CPU, from an FPGA/CPLD perspective. The Verilog HDL source files carry the digital logic circuit design for the CPU. The CPU is just one part of a microprocessor, which ...
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1 vote
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Testing an array of instances using an input file

The problem is that you are driving the same 4-bit input value to each instance of your Lat module inside the Lat_array module. ...
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1 vote
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Parameter binding error in Icarus Verilog

You have an if construct outside a procedural block (initial or always) That makes it a non-...
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1 vote
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Verilog port width larger than defined

A parameter value can be overridden when a module is instanced inside another module. Since in1 is 224 bits wide, and since 224 =...
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1 vote

Do wire/net type constructs in Verilog map to programmable interconnects/ switching matrix of FPGA?

well, of course the HDL code gets converted into connected logic, not only logic: What good would unconnected LUTs do? They'd not be representing the HDL functionality. So, yeah. That routing is part ...
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1 vote

Verilog help: .V to schematic

Verilog doesn't describe a circuit of logic gate as you want it. That's one possible mapping of a subset of Verilog functionality. But in general, verilog literally just describes the netlist as a ...
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