# Tag Info

18

the FPGA synthesizer ignores these code parts completely? Both Quartus (Altera/Intel) and Vivado/ISE (Xilinx) respect initial statements for synthesis (as do some others). You can use them to set default (power-on) values for registers and memories. There are as ever limitations. Not all FPGA families support setting a power-up value for a register. In ...

10

This code is effectively creating an inverter with its input connected to its output. If the propagation delay through the inverter is long enough you will get a "ring oscillator". The frequency of oscillation is determined by the delay through the inverter. So, if you have a free-running oscillator what will be the value of its output at any given ...

9

The problem is sending constant data stream without any pauses between symbols. The ASCII symbol 'S' has a value of 0x53, so it is sent over the wire as repeating pattern of 0110010101 which includes the start and stop bits. Because there is no pauses between transmissions, the receiving UART does not know which bits are the start and stop bits in the ...

9

Learning Verilog is one thing. It also good to learn digital design. Modern designs use clocks. The synthesis tool doesn't want to make something sensitive to two different edges. You should us a clock and either count or reset depending on the input. You should digitally detect the edge to count up. always @(posedge clock) begin KEY3_d1 <= KEY[...

8

In general, you should not be focusing on optimizing the implementation via the source code — the toolchain is much better at that than you are anyway. And specifying individual gates in the source code is pointless on an FPGA anyway — A function like (s_t > 9) becomes a single 4-input LUT in either case. Instead, focus on clarity and readability for ...

8

As others mentioned/explained, undefined behavior is not the same as 'randomness'. And I believe you misunderstood the meaning of always @(*) construct in your example code. Simulator perspective First of all, it doesn't mean that randomly flip the value of tempBit. It means that: 'Simulator may trigger this always block for any changes in the values (i.e., ...

7

They are equivalent. The width of all operands get extended to the size of the largest operand before any operation occurs. As long as the width of one of BC or AD is 16 bits wider than the value being shifted, then what you wrote is mathematically equivalent to $(BC + AD)×2^{16} = BC×2^{16}+ AD×2^{16}$ If the width of the largest operand is not wide ...

7

Get rid of the end before the else. The compiler is confused about where the first if ends. Also, always_comb doesn't allow outside processes to write left-hand side variables (vs. always @ *, which does) regardless, more than one driver the same wire type is not allowed. The always_comb boils down to an assignment for z, so trying to assign it again ...

7

Although the terminology sounds similar, there are big differences between a constant expression and a const variable. A constant expression is an expression whose operands are made up entirely of parameters and literals. Its value gets resolved as part of the compilation and elaboration process, before time 0. A const variable is a variable that is written ...

6

Can always @ (*) introduce randomness in FPGA? It's undefined behaviour. That can be random, but it's more likely to be a constant value, that might even be chosen during synthesis to optimize this structure away. "Undefined behaviour" means your synthesize can do with this what it wants, since it literally can't make things any worse. Setting the ...

5

In the Modelsim waveform display, you need to right-click on the output signal and change the data representation to unsigned. It's currently interpreting the 8-bit value as a signed integer.

5

Depends on the tool and the target architecture. It will sometimes for example infer a DSP48 (Xilinx) but that is not a given and sometimes you will get something built in the fabric (Which generally has a semi dedicated carry chain up a column, so this is quicker then you might expect). Why do you even care as long as it meets timing? If you want a ...

5

As an addition to Justmes answer (feel free to combine this into your answer): This is a UART Transmission of an S: This is what happens if you dont have an idle: And this part is what the receiver sees as a repeating 0xAA: edit: to be clear, i dont think this should be marked as the answer. This should just be an addendum to Justme's answer

5

r1 <= r1 is not required in any synthesiser, as it is in the definition of RTL. Since the logic is written under @posedge clk, it is implicit that the previous value of a the register r1 should be held in that clock cycle if r1 is not driven any value at that clock edge ie., in this case, if the condition cond1 is violated. This is true for the second ...

5

You can write a statement inside the combinational block like this: always_comb begin z = 42; if ( x == 0 ) z = some_value ; else if ( y == 1 ) z = some_different_value ; end This statement before the if statement executes if none of the statements in the if statement are true. It is an alternative method of writing this: ...

5

A good practice is creating a package with a set of global parameters used by your project that you can import. Putting them in a package avoids namespace collisions with other projects or external IP that you might have to integrate later. `define macros are global and have the problem with namespace collisions and file compilation order dependancies. const ...

4

In Verilog, assign can only be used with wire type variables. If you had declared it as output [7:0] detect or output wire [7:0] detect it would work fine (wire is implicitly inferred in the first declaration). This question is also relevant. Also bear in mind that initialisation like you have done here is not guaranteed to be synthesisable in an FPGA, and ...

4

A 3-input LUT is an 8-bit memory, and that memory can contain one of 28 = 256 different values. Each value represents one possible Boolean function of the three input variables. A 2-input LUT can contain one of 24 = 16 different functions. When you cascade two 2-input LUTs, you are effectively creating a temporary variable T that is a function of two of the ...

4

The conditions in an if-else if chain are evaluated sequentially, and once one of them matches, the other ones will not be checked. So when you have: else if (start) counter <= counter + 1; else if (start && stop) it sees that start is 1, and runs the counter + 1 assignment. It never checks if stop is also 1. To fix it, you have 2 options: ...

4

I found this post: Is it possible to create a working JK-flip flop using gate level description in Verilog Notice that the earlier question seems to be asking only about formally describing the JKFF in Verilog and simulating its behavior. While you seem to want to actually synthesize the device and implement it in an FPGA. These are two different problems. ...

4

SystemVerilog has the array assignment operator '{...} in addition to the concatenation operator {...}. Concatentation is for packed arrays - basically you combine multiple signals into a single bus. wire [7:0] a = {4'd7, 4'd14}; You can nest concatenation operators too. The following assigns the same value to b as was assigned to a in the previous example. ...

4

This is a workaround: Steps: Create a file with the extension gtkw. This file contains how you want the state variable to be displayed on the waveform. For your example it would be: 00 STATE0 01 STATE1 10 STATE2 Because you have used logic type which is 2 bits wide and have not encoded the state variables, SystemVerilog assigns the state variables the ...

4

Inputs are declared as reg and outputs as wire only in Verilog. In SystemVerilog, we use logic for 4-state simulation and bit for 2-state simulation. In Verilog, inputs are declared as reg because they are variables which store values during simulation. The value is stored in the inputs of type reg till it is overwritten by some other value. The datatype ...

4

According to the section "12.3.1 Port definition" in one of the revisions of the Verilog standard, a module includes [ list_of_port_declarations ] ; with the following syntax: list_of_port_declarations ::= ( port_declaration { , port_declaration } ) | ( ) port_declaration ::= {attribute_instance} inout_declaration | {...

4

Assuming: KEY input is already de-bounced Your board has flip-flops with asynchronous set/reset No other edge events will be added Then you could do this: always @(negedge KEY[3], negedge KEY[2]) begin if (!KEY[2]) begin // async reset mSEG7_DIG <= 0; end else begin // synchronous add mSEG7_DIG <= mSEG7_DIG + 1; end end However the ...

4

You can simplify the procedural block by using an implicit sensitivity list, always @* in Verilog and preferably always_comb in SystemVerilog. And you should not be using non-blocking assignments in combinational logic. always_comb case (sel) 2'b00 : out = a; 2'b01 : out = b; 2'b10 : out = c; 2'b11 : out = d; endcase Almost the same amount of typing ...

4

RTL is a style of coding where clocked elements are expressly implied. This is generally done because synthesizers are not generally designed to design state machines on their own. While they often shine at logic optimization, they are not sophisticated enough to design all the synchronous timing from an abstract description. HDLs such as VHDL and Verilog ...

4

While previous answer doesn't directly answer the question, it provides a common understanding of how RTL should be read regarding digital design topics, at least according to my engineering and teaching experience. Opposed to that, from slides at the first two links in your question, I got an impression of sloppily mixed concepts and terminology (note, that ...

4

That division operation works fine fine. It just treats everything as a truncated integer. However, be aware The clock is not a regular signal that runs through the logic fabric. Clock signals on FPGAs are distributed through one of the clock distribution networks on the FPGA in order to minimizes skew. There are only a limited number of these networks on ...

4

Intra-assignment delays in a Verilog always block should NEVER be used (NEVER!). There is no known hardware that behaves like this intra-assignment delay using blocking assignments. If I could take this out of the Verilog language I would, but I can't because of backward compatibility. In Verilog training, I always say, "if your mother and I ever catch ...

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