Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

Verilog is turned into logic through a process called synthesis. When targeting synthesis (rather than testbench code or esoteric use cases), a sub-set of the full language features will be used since the language can express features which do not map directly to physical gates.

Verilog can be used for many applications, from FPGA implementations, to ASIC design. The application can have a profound impact on how Verilog can be used.

Check out Stack Overflow documentation: http://stackoverflow.com/documentation/verilog/topics

Sometimes it is referred to as Verilog HDL. However it is not the same as VHDL.

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Code Language (used for syntax highlighting): lang-vhdl