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How to create a 400 MHz synced clock from 1200 MHz in Verilog?

Since you used the testbench tag, I assume this is purely for Verilog simulation only. If you want both edges of clk2 to be ...
toolic's user avatar
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2 votes
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Can generated events get placed before events already in the event queue in SystemVerilog?

The LRM section 4.7 Nondeterminism basically says that event regions are not queues--events scheduled in the region may be executed in any order. Your example is degenerate because the order your <...
dave_59's user avatar
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0 votes

Synthesizable system verilog code to find least number in an array

In general, when you want to apply an operation across an array of data that is presented all at once (in parallel), you should be thinking in terms of "binary tree" instead of "...
Dave Tweed's user avatar
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1 vote

Synthesizable system verilog code to find least number in an array

For loops in Verilog are unrolled - in other words every iteration of the loop corresponds to some piece of hardware. As a result you cannot have a synthesisable loop with variable number of ...
Tom Carpenter's user avatar
2 votes

I am calculating the sum and signed overflow on the addition of two signed numbers, but the overflow is not true in some cases. Can anyone correct it?

The bit you are calling overflow is actually the carry bit from the addition. It is equivalent to "overflow" only when adding unsigned numbers. When ...
Dave Tweed's user avatar
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