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According to the Verilator documentation If no language is speci􏰁ed, either by this 􏰂ag or +langext+ options, then the latest SystemVerilog language (IEEE 1800-2017) is used. In SystemVerilog it is legal to have one (and only one) continuous assignment to a variable. According to the Questa/Modelsim Documentation If you use the -sv argument with ...


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If what you say is correct then the answer is simple: Verilator is wrong, Modelsim is right. You can NOT use an assign with a reg as LHS variable type.


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Of course you can't do a continuous assignment to a register - that violates the whole concept of what a register is. A register samples the input at the clock edge.


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I realised the reason why readmemh wasn't working for me was that the size of the structure being written to has to be the same size as the data being read in. This may be a normal constraint or it could be down to my setup but it fixed the issue for me.


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In principle, the answer to your question is 'yes'. A synthesiser can treat an X value as a don't care, which can lead to better minimisation. In practice, though, this is a really bad idea. The fundamental issue is that simulation treats X values as 'unknown' or 'wildcard', which is not the same as the synthesiser interpretation. This means that an RTL ...


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Signed overflow occurs when the result of addition is too large for a given type to represent. This occurs when either: Addition of two positive integers result in a negative integer result (so the result msb - the sign bit - is 1 when it should be zero) or Addition of two negative integers result in a positive integer result (so the result msb is 0 when ...


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From reading these replies I am now realizing there is no set definition of how "testing" differs from "verification" in the industry. When working with HW design ("real" HW design, like stuff on PCB, not VHDL programming) we go through a verification&validation phase, and a production testing phase (actually just designing the production tests ...


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The simple answer is that Xilinx, to use your example, did not implement their flip-flops in Verilog. Their flip-flops are full-custom VLSI designs where the logic cells are highly optimized. However, we can get a notion of how Xilinx would accomplish this. If there is only one reset input signal for the cell, and we know that the actual implementation of ...


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Both synchronous or asynchronous resets in design are necessary for different reasons. It has been a religious issue for decades. How to implement a Reset Tree, then test all initial vectors and measure system response and latency is a matter of speed and system DFT philosophy. (design for testability) Thus specifications are needed before any ...


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I don't know why anybody would want this as the asynchronous reset would make the synchronous reset superfluous. It makes more sense to do this, but with two different reset signals, an asynchronous and a synchronous reset : always @(posedge clk, posedge async_reset) if (async_reset) q <= 1'b0; else // this is the clocked section ...


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I think the problem lies in this part always @(posedge CLK) begin if (Reset_L==0) SCURRENT <= A; else SCURRENT <= SNEXT; case (SCURRENT) A: Y<=9'b000000001; B: Y<=9'b000000010; C: Y<=9'b000000100; D: Y<=9'b000001000; E: Y<=9'b000010000; F: Y<=9'b000100000; G: Y<=...


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Time 0 initialization is not well defined in Verilog. Since r is defined as a wire, some simulators start all wires in the z state. Then if your testbench drives it with an uninitialized variable in the x state, there is a z to x transition at time 0. Your code is not using a named event. That requires declaring a signal with the event data type. You are ...


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Variables of the type 'reg' start simulation with the value of 'x'. Any assignment after that, also an initial assignment, will be seen as a change and will trigger the always @(r) statement. Thus your c can change at time 0. Having said al that: you code is behavioral and can not be synthesized as you have multiple drivers for `c. Additionally the ...


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As Joshua says, something is clearly wrong here. The synthesis tool has clearly optimized away your memory. Having had a quick readup on the ice40 blockram it seems to have registered output, so making the output combinatorial would force the tool to use a big bunch of registers instead of a blockram. Speculating a bit here, but I wonder if readmemh only ...


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Normally if my design shows a drop in resources it means that it actually 'optimized' something away; I suspect the same has happened here. Typical FPGA toolchains will cut everything away that does not directly or indirectly influence an output pin. Best way to check what Yosys is doing seems to include using the 'show' command: http://www.clifford.at/...


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As we have several people who say that it can't be done here is a behavioral solution :-) Note that in real hardware it can't be done this way. module pulse_double( input pulse, output reg double_pulse ); time time_rise,time_elapsed; always @(posedge pulse) time_rise = $time; always @(negedge pulse) begin time_elapsed = ...


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As oldfart correctly points out: This answer applies to verilog meant to actually define hardware only; for simulation models, see his answer! For example, if the input is a 1ns pulse, then I want the output to be 2ns pulse That's not among the abilities of verilog, as far as I can tell; since this is not a logical or clocked thing that you want, it's ...


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Thanks to Andrea Venturi for tip on the root cause. Indeed /bin/sh has very special meaming in Unix. For regular scripting /bin/bash should be used. Here how to fix all iCEcube2 scripts: $ cd <iCEcube2.2017.01>/synpbase/bin $ find . -type f -exec sed -i 's/\/sh/\/bash/g' {} \;


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If your board is in the database, Quasrtus should be able to populate the QSF file automatically. When configuring the project, were you able to pick your board from the list? Presuming that didn't work for some reason, as suggested on your another question, take a look at the doc for your board. Look for USER_LED0, for example (Ctrl-F works on this doc). ...


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You are changing the stimulus on the falling edge of the clock, such as "start assigned '1'". The state changes on the next rising edge of the clock, such as "entering Water in state". The way your code is written makes it impossible for them to happen simultaneously. However, your inputs should not change at the same time as the clock edge that changes the ...


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If you've a blocking assignment statement it'll be executed in the order that's specified in a sequential block. For example, initial begin x=#5 a; y=#5 b; end The a is assigned to x at simulation time 5, while b is assigned to y at simulation time 10. Now consider nonblocking assignment statements with intra-assignment delays that follow in a sequential ...


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Nonblocking assignments simply defer the actual update of the value until all of the statements in the current always block are evaluated. It has the appearance that all of the statements run "concurrently" or "in parallel", but if this was actually the case, it creates an ambiguity: what happens when you assign the same reg two different values in the same ...


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Your course is being a bit loose on the details. Something that makes VHDL and Verilog somewhat tricky is that they were originally designed as languages for describing hardware for simulation. They were then later re-used as languages to describe hardware for synthesis. To understand HDL simulation there are first a couple of basic concepts we must ...


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You have to separate the software execution semantics in simulation from the hardware semantics in synthesis. Verilog/SystmeVerilog gets used for both. And sometimes the terminology gets reused in different ways, especially the word sequential. Each always block represents a concurrent process or behavior based on the procedural code you write associated ...


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