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6

You can find and fix the syntax errors. They are usually quite simple. In this case, you may need a better VHDL compiler to help you diagnose them ... ghdl ( https://github.com/ghdl/ghdl documented at https://ghdl.readthedocs.io/en/latest/) reports ghdl -a aritmetico.vhd aritmetico.vhd:35:8:error: invalid use of UTF8 character for ' presumably at F1<= ‘0’...


3

Your assignment statement: temp2<=std_logic_vector(resize(to_sfixed(temp2_32,3,-28),1,-14)); should cause a simulation error: ghdl -r resize_function ./resize_function:error: bound check failure at resize_function.vhdl:12 in process .resize_function(foo).P0 ./resize_function:error: simulation failed This should be caused by the semantics of the type ...


3

No, they are not exactly equivalent. The first variation if (clk'event and clk='1') then only works correctly if the previous state of the clock was in fact '0'. This works fine in most cases, but won't catch unusual cases, such as when the previous state was 'U', 'W', 'X' or 'Z'. The second variation uses rising_edge()1, which specifically checks whether ...


3

In your testbench you are not asserting the reset_n signal at all. You should make reset_n = '0' for several clock cycles, then deassert it to '1' and then continue with the rest of the simulation. In the current simulation rx_state never receives an initial value and that is why the rx output signals are undefined


2

The problem here is that the tech stack (knows as a flow) tends to be a trade secret and heavily NDA'd. As a beginner asking an open-ended question, perhaps the most useful answer is a list of places to look for more information. The two big software vendors are Cadence and Synopsys. Both of them offer a full flow from RTL (and earlier) through to the ...


2

I don't think such large ICs are designed directly in Verilog, no more than large software projects are written in assembly. I suspect the big makers, like Intel and AMD, have specialist compiler-like software that generates Verilog from much more high-level descriptions, such as register transfer languages.


2

Delta cycle delay on addr ... you are writing to the PREVIOUS address so you write 0 to addr UUUU.... ditto reading from the previous address. Either think through the pipeline more carefully, or compute addr before the clock edge (i.e. outside the clocked process in a concurrent assignment), or make addr a variable instead of a signal. The phase delay on ...


2

The problem is solved. I fix the code for counter_modK.vhd. Now instead of puts rollover signal to high when the counter state is K-1, rollover gets high when counter state is K-2 and I use rollover to increment the counter or reset its internal state. The code is: counter_modK.vhd: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ...


1

Unclear what you are trying to achieve. First, it seems like an odd restriction for Quartus to restrict state types to enumerations instead of other discrete types like integer or unsigned. But... Do you really have 231 discrete states? Or is range 34 to 50 a single state? If you need to remain in that state for 17 separate events, consider a state and a ...


1

Here is the final code, well final as of this moment. -- VHDL created by Arius, Inc copyright 2020 -------------------------------------------------------------------------------- -- Company: Arius, Inc -- Engineer: Rick Collins -- -- Create Date: 2020/10/25 03:23z -- Design Name: Alarm -- Module Name: Blk_mem -- Project Name: OVB_Alarm -- -- ...


1

Now that we have a testcase, ghdl reports: ghdl -a --std=08 VHDL_test.vhd VHDL_test.vhd:26:17:error: can't match 'nxt_cnt_a' with type std_ulogic VHDL_test.vhd:26:17:error: target is not a signal name Which is a little less confused than your simulator, that the error is to do with mixing different types within an aggregate. (but see edit below : this is no ...


1

(Carry_Out_a, nxt_cnt_a) <= RESIZE(Count_a, nxt_cnt_a'length + 1) + 1; I will use a variable Count_a_new of length nxt_cnt_a'length + 1. Since nxt_cnt_a'length is equal to Cntr_Width + 1, nxt_cnt_a'length + 1 is equal to Cntr_Width + 2. Declaration of the variable: variable Count_a_new : unsigned((Cntr_Width + 1) downto 0) := (others => '0'); Then, I ...


1

There is no concept of hardware software co-simulation on a general purpose, average CPU, since the CPU does not have the processing power to emulate hardware real-time in a fashion that is timing-accurate. You want to emulate hardware in a fashion that is timing-accurate since you want the software to run on the hardware and be able to debug it a timing-...


1

Both implementations are possible. The choice of the implementation depends on the optimization of the design software. However you can control the way it is implemented by using directives. First, in the following example in Quartus II the software design has chosen to use memory: library IEEE; use ieee.numeric_std.all; use IEEE.STD_LOGIC_1164.ALL; entity ...


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