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4 votes

VHDL: My counter increments by 2. Why?

You have latches everywhere due to unassigned signals throughout the if-else statements within your case. For example, even your ...
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2 votes

VHDL: How to use records as PORTS with IN and OUT parameters?

It depends on if it is Design or Verification. For Design until your vendors support VHDL-2019 interfaces you need one record for in and one record for out. For verification is better with VHDL-2019 ...
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