Your minimalist TCP/IP implementation in an FPGA may be a soft core processor running some code.
The bare essence of this is that TCP/IP requires a big and (relatively) slow state machine. In general, you make efficient use of logic (compared to a processor) if you're implementing (relatively) small and fast state machines, or better yet, arithmetic that ...
I'm not quite certain to understand what you are trying to do here. Maybe there is a bit of a XY problem in the first place. Nonetheless, I'll try to answer questions we have so far.
Strings are defined by standard as:
type STRING is array (POSITIVE range <>) of CHARACTER;
and positive is defined as:
subtype POSITIVE is INTEGER range 1 to INTEGER'...
My preference is to keep my synthesis code as simple as possible. So I keep error checks as independent as practical from my logic code. So I use choice number 2.
If I want error checks, I use an assert of the form (preferably concurrent, but in your case maybe sequential):
assert not (is_x(EXPECTED_ACK_STATE_MATCHED(i)) or is_x(EXPECTED_MSG_CODE_MATCHED(...
Rewriting in non-VHDL-2008 style (output port should become buffer, and add explicit level tests to std_logic signals)
entity Integrator is
port( Input : in integer;
Output : buffer integer := 0;
Sample : in std_logic; --clock enable
Either of the ways you have written it is perfectly correct.
I don't believe that testing for values other than '0' or '1' is synthesizable in any devices I have ever used. So it doesn't make any difference with regard to synthesis and implementation.
Testing for things like 'U' or 'X" can be useful for debug in simulation. Its certainly not required, ...
You can have a look at FPGA Cores. They do Ethernet cores with TCP and more without processor. Maybe you can get some ideas from that. I have used them in several projects. Probably Xilinx only.
They are free to download. Cheers.