As Marcus Müller pointed out, the compiler can ignore all logic as if((x+y) / 49 > 200) will never render true with the limited integers. I have made a new test with some logic that the compiler has to respect:
Example A V2:
entity PipelinePoc is
Port ( clk : in STD_LOGIC;
led : out std_logic_vector(0 downto 0)
It matters for the same reason as programmers write in the highest level language that is suited to the problem domain (all else being equal).
Programs (and hardware designs) are written mostly for other humans to interpret and only incidentally for the synthesis tools.
Basically everyone on non toy projects spends more time reading other peoples code ...
Incoming signals that are asynchronous to your FPGA must be synchronized to your FPGA's clock domain by running it through a chain of at least two flip flops before using it with any synchronous logic. Or else nothing guarantees that the incoming asynchronous edge does not land on an FPGA clock edge resulting in metstability. The chain of flip-flops reduces ...
When there is no assignment, the last value of the FF is kept in a synchronous process, in an asynchronous process a latch is inferred.
When there are several assignments to the same signal in the same process, the last one is applied.
if rising_edge(clk) then
if X then
if Y then
reg <= '1';
reg <= reg;
I don't know if it's still relevant, but: an IO-Link Master stack can be hardcoded just to read the sensor data/parameters. You would still need to read the spec or have experience with IO-Link to implement it but it's doable on an FPGA since basically it's just a serial protocol.