8
votes
Is there any way to know how real discrete components are being connected to each other using logical gates?
When you design in an HDL, you are not actually designing circuits. You are designing logic. Another program (typically) then takes this logic and performs the circuit synthesis based on your target ...
- 680
4
votes
Is there any way to know how real discrete components are being connected to each other using logical gates?
passive components are being connected to each other using logical
gates?
It depends on the process (TTL or a mosfet based design) in an IC. If one is building the gate on the bench then descrete IC'...
- 78k
4
votes
Accepted
Why do I still have latches even though I include everything in sensitivity list?
Generally, latches are inferred when an if else or case type of statement has a missing if-else or case somewhere. In other words it's incomplete.
I think you might need to check what possible values ...
- 2,501
2
votes
Is there any way to know how real discrete components are being connected to each other using logical gates?
The question mentions VHDL and gate level primitives. However, VHDL doesn't provide support for gate level primitives.
Whereas the Verilog language does support gate level primitives. Gate Level ...
- 1,504
2
votes
Is there any way to know how real discrete components are being connected to each other using logical gates?
VHDL is a hardware language that is oriented toward creating logic. It knows about logical functions and connections between them (wires), and not much else. It isn’t inherently aware of transistor-...
- 51.1k
2
votes
Accepted
Drawing a Visual Hardware Representation for VHDL Code
Your design has 2 flipflops. The first flipflop is needed to store r_switch_1. The second flipflop is needed to store r_LED_1. The second flipflop will toogle as soon as there is a falling edge at ...
1
vote
Accepted
How to use VHDL to shift 2D array?
As long as you're only moving data on the second (horizontal) axis in matrix_5x5_Img you could make matrix_5x5_stdv an array of arrays with elements of std_logic_vector, allowing slice names:
...
- 292
1
vote
VHDL modular multiplication always resulting 0 in simulation
The user user16145658 posted the following comment:
Processes suspend and resume in wait statements, here the implicit one
as a final statement with the sensitivity list defined for the
process. ...
- 2,677
1
vote
Drawing a Visual Hardware Representation for VHDL Code
I think you are not totally correct. Your code is not only a DFF.
Your p_Register process also has some logic.
It seems that it needs r_switch_1 to perform a "AND" with i_switch_1, so the ...
- 433
1
vote
When I try to simulate VHDL code, the signals do not work, losses, show a orange color
Apparently you try to simulate your logic without applying a clock signal. All your logic depends on the input clock. Therefore the outputs are necessarily all undefined (...
- 2,541
Only top scored, non community-wiki answers of a minimum length are eligible