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38

Doing a remainder operation in serial fashion is actually quite easy. The key assumption is that the data comes in MSB-first if it's serial. You only need N states to compute a remainder modulo N. Start in the "0" state and if you end up in the "0" state after the last bit (it doesn't matter how many bits there are), the remainder is zero. simulate this ...


27

Adding to @Anonymous's answer, there are designs you can build which can damage the fabric of an FPGA. For starters if you build a very large design consisting of huge quantities of registers (e.g. 70% of the FPGA) all clocked at nearing the FPGAs maximum frequency, it is possible to heat the silicon considerably. Without sufficient cooling this can cause ...


24

Was an ASIC Design Verification Engineer at Qualcomm. In the most simple way I can explain it: Testing: Making sure a product works, after you've created the product (think QA). Verification: Making sure a product works BEFORE you've created it. They're both testing, just that verification is more complicated because you have to figure out a way to test ...


23

The standard is well designed and there are subtle details that ease implementation, for example, when rounding, the carry from the mantissa can overflow to the exponent. Or integer comparisons can be used for floating point compares... But, an FPU is a big heap of combinatorial mess; besides adding, multiplying, dividing, there are barrel shifters to align ...


23

Those parts of VHDL exist for use in testbenches. Being able to simulate a VHDL design under a VHDL testbench is an essential step in the VHDL development process. Verification is proving a design under a testbench that checks the design for expected behaviour and complains about deviations from it. Verification is always recommended, even for small or tiny ...


20

Short answer: use SystemVerilog, but learn also VHDL. Avoid Verilog-2001 if you can. Very long answer: for the moment, I assume by Verilog you mean Verilog-2001 which is probably what also most other answers assume. The best suggestion would probably be to learn both, but use neither (more on this at the end of the answer). The main differences can be ...


19

Triplication means (as noted) to make 3 of everything. It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the erroneous result circuit is reset. For this to work within a single device, partial reconfiguration in the FPGA is required. The reason this is necessary in SRAM ...


18

the FPGA synthesizer ignores these code parts completely? Both Quartus (Altera/Intel) and Vivado/ISE (Xilinx) respect initial statements for synthesis (as do some others). You can use them to set default (power-on) values for registers and memories. There are as ever limitations. Not all FPGA families support setting a power-up value for a register. In ...


16

You can also design a state machine if the data comes LSB-first: The existence of such a deterministic finite automaton (DFA) directly follows from the other answer, which describes the DFA for MSB-first. Because languages accepted by DFAs are regular and regular languages are known to be closed under reversal (e.g. see here), there must be a DFA which ...


14

What you are looking for is called external names (or hierarchical names) in VHDL. They can be used to circumvent scope/hierarchy visibility. The syntax is like the example below. <<signal path_name : std_logic_vector(7 downto 0)>> You can also access constants and variables with external names. You have to change the type in the external type ...


14

Schematic design is only useful when you're only tying together a few off-the-shelf modules (counters, adders, memory, etc). But implementing an actual algorithm (say, a cryptography hashing algorithm) is nearly impossible to do without an HDL (like VHDL or Verilog), since there's no way to describe a system at a behavioral level with schematic symbols. ...


14

I'm a developer and maintainer at 'The PoC Library'. We try to provide such a library composed of packages (collection of new types and functions) and modules. It comes with common fifos, arithmetics, cross-clock components, low-speed-I/O components and a Ethernet/IP/UDP stack (next release). As @crgrace described, it's quite complicated to design modules, ...


14

A half-latch is a gate with positive feedback implemented with a weak pull-up transistor: simulate this circuit – Schematic created using CircuitLab When the input is actively driven, it overrides the signal coming from the weak pullup. When the input is in Z-state, the weak pullup can keep the logical "1" at the input (and "0" at the output) ...


13

Use Yosys, the free and open source awesomeness HDL Synthesis Toolbox with extra doses of being cool (and free) (and faster than current-gen Vivado) (did I mention Free as in speech & beer?) (and awesome)! Get yosys, and the xdot utility (often part of a package called python-xdot) as well as graphviz. Then, do something like in a verilog file (let's ...


13

If you just want to multiply two numbers and they suit the DSP block then the * operator should infer a DSP block. If not, send the synthesis tool back :) However, to take advantage of the more complex combinations of the DSP functionality often requires a direct instantiation of the block and configuring of its parameters. Examples of things which may ...


13

It's a bit complicated and involves a lot of software. Initially, you write code in a hardware description language such as Verilog or VHDL. This, along with timing and location constraints, make up the input of the FPGA toolchain software. The toolchain is a series of software programs that transform the HDL description of the design into a binary ...


12

My career for last 13 years was 80% ASIC and 20% FPGA. VHDL was used for the 1st 3.5 years and the rest were Verilog. I didn't find switching to Verilog difficult, and for location (Silicon Valley) & speed reasons I only code in Verilog today. Also, I do a lot of Async interfaces, latches and gate level semi custom designs for performance, so VHDL has ...


12

or_reduce is what you want, and it is available in std_logic_misc. Supported by both A and X for FPGAs.


12

I will leave it to an LRM expert to provide a more detailed answer, but in short, your approach should be valid - I ran a quick test with a recent version of Quartus, and it handles '-' like it's supposed to - the logic generated is reduced as expected when the output is defaulted to '-' ('X' works too, by the way). More on the approaches you listed: Not ...


12

You're basically coding a whole bunch of 4-input multiplexers, so you could either write a function or create a submodule that you instantiate for each one. function map4 (sel: in std_logic_vector (1 downto 0); constant v0, v1, v2, v3 : in std_logic_vector (3 downto 0)) return std_logic_vector is begin case sel is when "00" => return ...


12

Two ways are commonly used: Stop the clock (or clocks). That way there are no more events, and the simulation stops. Sometimes, there is a signal (for instance called done) that turns of the clock generator. The testbench asserts the done signal when all tests are completed. Report a failure. This is not so elegant, but many people use it. A severity of ...


12

Optimizing to this level will break your heart. The result could change because of the technology of the FPGA you're using, other factors in the FPGA, but also because of factors outside of your control, including the fitter's random number seed. Having said that, I believe that option 3 will be the best. Options 1 and 2 have a comparator/OR gate going ...


12

FPGAs have tri-state outputs : sda <= 'Z' when dout='1' else '0'; There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor. VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs. You can write sda <='H'; in the test-bench to ...


11

Here is a little overview on chip internal buses, which are suitable for FPGAs: Advanced Microcontroller Bus Architecture (AMBA) from ARM Ltd. Current version: 5 Specifications Further reading: Wikipedia Commonly known buses in that family: Adavance Peripherial Bus (APB) Advanced High-performance Bus Advanced Extensible Interface (AXI) Variants: AXI-Lite, ...


11

By default, Quartus II used to set unused pins as outputs driving low. This wasn't good as you can imagine - one wrong pin constraint and a used input pin could be wrongly considered unused and be driving a shorting low onto the input signal. In more recent versions, it was changed to the sensible 'as input tri-stated with weak pull-up', which saved me ...


10

I don't see a synchronizer on the rx data line. All asynchronous inputs must be synchronized to the sampling clock. There are a couple of reasons for this: metastability and routing. These are different problems but are inter-related. It takes time for signals to propagate through the FPGA fabric. The clock network inside the FPGA is designed to ...


10

Yes, it's because you are using the "silicon" oscillator. The basys2 board also provides a socket for a crystal oscillator. If you plug in a crystal oscillator and use its clock signal the jitter is gone and the VGA image will be fine. I have tried it myself. BTW: The manual tells you about that: The primary silicon oscillator is flexible and ...


10

16 bits multiplied by 4 bits can become, at most, a 20 bits number, this is apparently the size implicitly created by VHDL for storing the intermediate result of the multiplication. When this implicit 20 bits number is assigned to a 16 bits array, the last 4 bits are lost. And that's why Brian Drummonds's VHDL simulator complained about bound array error. ...


10

VHDL is used in ASIC and FPGA development, as is Verilog. Pretty much all commercial chip design is done in one of those two. There's not so much a magic machine as a pipeline of large expensive pieces of software. The flow looks like this: humans write VHDL, then simulate in a program such as Modelsim to validate design. this is converted to a gate level ...


10

The sensitivity list is mainly a concept used by simulator to schedule the execution of processes. A synthesis tool will usually discard the sensitivity list. What are the results when running the above code snippets through a synthesis tool? The implementation without 'event will infer a latch, because that's what a synthesis tool "sees" when looking at the ...


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