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40 votes
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VHDL interview question - detecting if a number can be divided by 5 without remainder

Doing a remainder operation in serial fashion is actually quite easy. The key assumption is that the data comes in MSB-first if it's serial. You only need N states to compute a remainder modulo N. ...
Dave Tweed's user avatar
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28 votes
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VHDL that can damage FPGA

Adding to @Anonymous's answer, there are designs you can build which can damage the fabric of an FPGA. For starters if you build a very large design consisting of huge quantities of registers (e.g. ...
Tom Carpenter's user avatar
23 votes

VHDL: Why is it hard to design a floating point unit in hardware?

The standard is well designed and there are subtle details that ease implementation, for example, when rounding, the carry from the mantissa can overflow to the exponent. Or integer comparisons can be ...
Grabul's user avatar
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23 votes
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Why do non-synthesizable commands even exist in VHDL?

Those parts of VHDL exist for use in testbenches. Being able to simulate a VHDL design under a VHDL testbench is an essential step in the VHDL development process. Verification is proving a design ...
TonyM's user avatar
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19 votes

what is triplication on fpga?

Triplication means (as noted) to make 3 of everything. It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the ...
Peter Smith's user avatar
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18 votes
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FPGA register initialization

the FPGA synthesizer ignores these code parts completely? Both Quartus (Altera/Intel) and Vivado/ISE (Xilinx) respect initial statements for synthesis (as do some others). You can use them to set ...
Tom Carpenter's user avatar
16 votes

VHDL interview question - detecting if a number can be divided by 5 without remainder

You can also design a state machine if the data comes LSB-first: The existence of such a deterministic finite automaton (DFA) directly follows from the other answer, which describes the DFA for MSB-...
ComFreek's user avatar
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15 votes
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What is a "half latch" in an FPGA?

A half-latch is a gate with positive feedback implemented with a weak pull-up transistor: simulate this circuit – Schematic created using CircuitLab When the input is actively driven, it ...
Dmitry Grigoryev's user avatar
14 votes

How can I generate a schematic block diagram image file from verilog?

Use Yosys, the free and open source awesomeness HDL Synthesis Toolbox with extra doses of being cool (and free) (and faster than current-gen Vivado) (did I mention Free as in speech & beer?) (and ...
Marcus Müller's user avatar
14 votes
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What is the standard way to halt a VHDL testbench after a certain time period?

Two ways are commonly used: Stop the clock (or clocks). That way there are no more events, and the simulation stops. Sometimes, there is a signal (for instance called ...
Philippe's user avatar
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12 votes

Are there any standard FPGA internal buses?

Here is a little overview on chip internal buses, which are suitable for FPGAs: Advanced Microcontroller Bus Architecture (AMBA) from ARM Ltd. Current version: 5 Specifications Further reading: ...
12 votes
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Altera FPGA I/O weak pull ups

There are two ways of doing it. 1. Pin Planner The first approach is in the Pin Planner tool. This is the GUI that allows you to select which pin goes where. From the main window with your project ...
Tom Carpenter's user avatar
12 votes
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FPGA: count up or count down?

Optimizing to this level will break your heart. The result could change because of the technology of the FPGA you're using, other factors in the FPGA, but also because of factors outside of your ...
pscheidler's user avatar
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12 votes
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VHDL: What is correct way to model open collector output for FPGA?

FPGAs have tri-state outputs : sda <= 'Z' when dout='1' else '0'; There are also sometimes optional internal pull-ups, but they are not meant to drive ...
Grabul's user avatar
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11 votes
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What does the FPGA do with unreferenced I/O pins?

By default, Quartus II used to set unused pins as outputs driving low. This wasn't good as you can imagine - one wrong pin constraint and a used input pin could be wrongly considered unused and be ...
TonyM's user avatar
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10 votes

VHDL that can damage FPGA

Code is not a right word in this context. While Verilog or VHDL look like program, the output of the compiler is a configuration which is loaded into the FPGA chip forming electronic circuit within it....
Anonymous's user avatar
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10 votes
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Ranged vs Non-ranged Integers in VHDL

It depends, but it is almost always preferable to specify the range. For illustration, consider this example: ...
Blair Fonville's user avatar
10 votes
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Is this matrix-vector multiplication function in VHDL parallelized?

In 'hardware' (VHDL or Verilog) all loops are unrolled and executed in parallel. Thus not only your inner loop, also your outer loop is unrolled. That is also the reason why the loop size must be ...
Oldfart's user avatar
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10 votes
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Clock Phase Shift Not Working on FPGA

When there is a 90° phase shift between two 5MHz clocks, that means there is a 50ns skew between them. If you divide those two clocks by 5000000 using two instances of the same counter structure, you'...
Nipo's user avatar
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9 votes

Reverse engineering the manufacturer's programming sequence of an FPGA

It is certainly possible to program (using and HDL) and do useful tasks on FPGAs without using any third party IP blocks - if that is what you meant. However you do still have to use the vendors ...
John's user avatar
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9 votes
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Reverse engineering the manufacturer's programming sequence of an FPGA

There may be a misunderstanding about what 'IP' means. It's possible to program the fabric of an FPGA, that is the programmable LUTs and things, from the ground up. However, the bits and gates and ...
Neil_UK's user avatar
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9 votes

Is it good practice to always assign initial value and reset signals in digital design?

I would say that there are a couple of different ways that you could argue that. Not sure what the 'best' method is in general, it's going to be dependent on what you're trying to accomplish. It's ...
alex.forencich's user avatar
9 votes
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in what order does a VHDL program run in an FPGA

You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" ...
Ale..chenski's user avatar
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9 votes

VHDL: is there a way to create an entity into which constants can be passed?

Add a generic clause to your entity. It allows you to pass in e.g. constants: ...
Paebbels's user avatar
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8 votes

VHDL vs. Verilog

I went for VHDL, mostly because I know C really well and found that trying to write verilog tended to have me writing as if I was targeting a CPU not describing hardware. Very annoying to write a ...
8 votes
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Handling inferred clocks during RTL Synthesis

You have added an FPGA tag, so I will answer from an FPGA perspective. If you are creating an ASIC or using some other flow, a different answer might apply. 1. Why ...
scary_jeff's user avatar
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