5
votes
Accepted
Does VHDL allow a std_logic_vector port with no bounds?
This unconstrained declaration is valid, but it depends on another definition outside this module. Note that no "generic" declaration is required for this simple D Flip-Flop example:
...
- 6,882
3
votes
Accepted
How to implement do-while loop in VHDL?
While less compact than do-while, VHDL does contain the loop-...
- 17.9k
2
votes
Accepted
How to achieve signal gating with trigger input
You can achieve the pulse-gating in your requirement, using a negative level-sensitive latch and an AND gate. Modified version of typical Clock Gating cells found in ASIC libraries.
If you describe ...
- 10.4k
2
votes
Accepted
How to apply two NOT gates sequentially in VHDL?
Well, what you want is some delay, not really NOT gates.
What do you want that delay for? Adding random gates isn't a reliable solution, logic synthesis will optimize equations as needed. Depending on ...
- 3,174
2
votes
How to implement do-while loop in VHDL?
You could use an infinite loop and exit at the end condition; that's the clearest way.
Otherwise put the code in a function/procedure (if feasible) and call it once before the while and once inside ...
- 7,676
2
votes
How to design interfaces for memory hungry circuits
You have an "external" memory interface either way.
The array in VHDL is referenced by an index, and you pass the index you want to read or write through a ...
- 10.3k
1
vote
Error (10500): VHDL syntax error at setpoint.vhd(37) near text "when"; expecting ";"
when - else construct is a concurrent statement in VHDL. You cannot use it inside a procedural construct like process (). It has to be described outside ...
- 10.4k
1
vote
(others => '-') in VHDL
You have a very subtle problem.
The short answer is, for this problem, do not use the package ieee.numeric_std_unsigned.
If you look in ...
- 639
1
vote
Synthesize of "REAL VARIABLES" in Vivado 2020.1
To determine whether a given construct is synthesisable in Vivado, you can refer to the Vivado Design Suite User Guide: Synthesis (UG901) document. This includes a full breakdown of which Verilog, ...
- 56.9k
1
vote
Accepted
4 input multiplexer in VHDL
Repeat the lines:
library IEEE;
use IEEE.std_logic_1164.all;
Like this (before the second entity):
Which works when elaborating 'mux4':
- 6,882
1
vote
Vivado: Design failed to meet timing requirements. Is it because of ifs?
There is a simple mistake here: the XAUI block is clocked with a 10 MHz clock from a PLL (that is instantiated by the clock wizard), but the reset signal is ...
- 10.3k
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