Misundertanding in the working of for loop
When your count = 4, unroll the loop to understand what happens in the hardware. You assign multiple vales to SDATA_ADC:
SDATA_ADC <= ADDR_DATA (15);
SDATA_ADC <= ADDR_DATA (14);
SDATA_ADC <= ADDR_DATA (0);
But only one serial data will be sent via SDATA_ADC in that clock edge, ie., ADDR_DATA (0).
Just for completeness, answer is already in the comments
An entity of a VHDL component has to match the filename. Therefore you should either rename the entity to adder1 or the file to signed_adder.vhdl.
As mentioned there are other potential issues in your code
a_sig <= UNSIGNED(a);
The compiler should complain here because you try to assign an 8bit ...
For the Finite State Machine (FSM), you need to clearly define your inputs, outputs, states, and transitions.
And for VHDL-2008, sensitivity lists are a thing of the past (they used to cause lots of bugs due to simulator/synthesiser mismatches). They have been replaced with process(all).
This is an example of state names you could use without using a ...