# Tag Info

23

Those parts of VHDL exist for use in testbenches. Being able to simulate a VHDL design under a VHDL testbench is an essential step in the VHDL development process. Verification is proving a design under a testbench that checks the design for expected behaviour and complains about deviations from it. Verification is always recommended, even for small or tiny ...

18

the FPGA synthesizer ignores these code parts completely? Both Quartus (Altera/Intel) and Vivado/ISE (Xilinx) respect initial statements for synthesis (as do some others). You can use them to set default (power-on) values for registers and memories. There are as ever limitations. Not all FPGA families support setting a power-up value for a register. In ...

10

When there is a 90° phase shift between two 5MHz clocks, that means there is a 50ns skew between them. If you divide those two clocks by 5000000 using two instances of the same counter structure, you'll get two 1Hz signals with 50ns skew between them (which is roughly 0° at 1Hz). I doubt you can see this with bare eyes. So to me, this test gives you no ...

9

There is an alternative to passing generics through all levels of the hierarchy: declare the relevant quantities in a package, and "use" that package in every unit that needs it. You can do a little better than a constant data_width. package bus_types is constant DATA_WIDTH: natural := 8; subtype DATA_BUS is std_logic_vector(DATA_WIDTH - 1 ...

7

You can create an integer generic on the instantiated component and pass it the loop control variable value. Then your instance can use the generic value to distinguish itself from the other instances. component REG port(D,CLK,RESET : in std_ulogic; Q : out std_ulogic); end component; begin GEN_REG: for I in 0 to 3 generate ...

6

Declare data_width as generic in top module. Map this generic to corresponding generics in the submodules. For eg: entity Top is generic (data_width: integer := 32); port (...); end entity; architecture Structure of Top is component CompA generic (data_width: integer := 8); port (...); end component; begin u1: CompA ...

6

This is not specific to VHDL, but generally here's how to interpret compiler error messages: Error (10500): VHDL syntax error at clothes_washer.vhd(22) near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable" The keyword "Error" means a serious problem that ...

6

You cannot put a 22uF capacitor directly on the output of the op-amp, it will oscillate. Very low capacitances (like up to ~50 pF) are okay in your (worst-case) application as a voltage-follower. As it says in the datasheet: Capacitive loads which are applied directly to the output of the amplifier reduce the loop stability margin. Values of 50 pF can be ...

6

Your minimalist TCP/IP implementation in an FPGA may be a soft core processor running some code. The bare essence of this is that TCP/IP requires a big and (relatively) slow state machine. In general, you make efficient use of logic (compared to a processor) if you're implementing (relatively) small and fast state machines, or better yet, arithmetic that ...

5

The problem is statements: if(rising_edge(Set_Button) and Set_Button = '1') . . if(rising_edge(Enable_Button) and Enable_Button = '1') When you synthesise this code, the synthesiser recognises these two signals as the clocks in your design. These are also Input Ports in your module. If these signals were truly clock inputs in your design (which I don't ...

5

Your error message is: Error (10500): VHDL syntax error at QA4.vhd(43) near text "0"; expecting ")", or "," This is reporting that the error is detected when parsing line 43. The problem could be before that line, but not usually after it. Counting the lines in your source, line 43 (where the error is detected) is: xDist <= ...

5

Asynchronous delays are effectively impossible in FPGAs. Running off anything but the system clock as a clock is fraught with difficulty. The correct way to do it, and by correct I mean a way that the timing and PAR tools will work with you rather than you having to fight them, is to use a system wide high speed clock, and use clock enables to qualify when ...

4

The problem is solved. I fix the code for counter_modK.vhd. Now instead of puts rollover signal to high when the counter state is K-1, rollover gets high when counter state is K-2 and I use rollover to increment the counter or reset its internal state. The code is: counter_modK.vhd: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ...

4

The Vivado synthesiser is smart. You have to declare the operands as signed. If the operands are unsigned, explicitly type cast all of them to signed and then simply multiply using *. It should infer a signed DSP multiplier on synthesis. If it's not inferring automatically (can be due to multiple reasons), then you may have to use USE_DSP attribute to force ...

4

Incomplete answer. First note this is a block, not a process. A block wraps some declarations and concurrent statements (which can include processes) together, without exposing those details to the wider design. But the problem here is not the block; it's that these Asserts are written in PSL, Property Specification Language, which is used to extend VHDL's ...

4

As BrianDrummond pointed out in the comment section, I was driving the same pins in my source file multiple times. Although this is only in simulation as it is during the test phase, and not on a FPGA board, I am relatively new to FPGAs / VHDL. I have around 15 instances of the same component in my top level file and I copy and pasted each instance ...

4

Your if statements are nested, so if Run_Reset = '1', the entire process is skipped, and if Run_Reset = '0', the counter is reset and the increment code is skipped. The counter can never take on any other value than zero.

4

You can simplify the procedural block by using an implicit sensitivity list, always @* in Verilog and preferably always_comb in SystemVerilog. And you should not be using non-blocking assignments in combinational logic. always_comb case (sel) 2'b00 : out = a; 2'b01 : out = b; 2'b10 : out = c; 2'b11 : out = d; endcase Almost the same amount of typing ...

4

RTL is a style of coding where clocked elements are expressly implied. This is generally done because synthesizers are not generally designed to design state machines on their own. While they often shine at logic optimization, they are not sophisticated enough to design all the synchronous timing from an abstract description. HDLs such as VHDL and Verilog ...

4

While previous answer doesn't directly answer the question, it provides a common understanding of how RTL should be read regarding digital design topics, at least according to my engineering and teaching experience. Opposed to that, from slides at the first two links in your question, I got an impression of sloppily mixed concepts and terminology (note, that ...

4

The value of 0xFFF on the output is correct. Multiplying 0x001 and 0xFF6 as 12 Bit signed integers results in 0xFFFFF6. Now you specify the output width as 12 Bit - and the uppermost 12 Bit of the result are 0xFFF.

4

My thoughts It's good practice to always mention a default value to generic during entity declaration because it makes sure that the entity can be synthesised and simulated as an individual module if needed. Whatever default generic in the entity declaration can be overriden during component declaration in a top module*. If there was a default generic in ...

4

Latches have to properly timed on its paths to obtain the intended latching behavior. Latches have a combinatorial feedback and hence its timing cannot be correctly analysed by an FPGA synthesiser. This is one reason why combinatorial loops are said to be 'bad' and unpredictable to synthesise on an FPGA in HDL. Out of curiosity, I tried both versions of your ...

4

Assertions are supported in VHDL at different severity levels ($\color{red}{\text{Error}}$, $\color{blue}{\text{Note}}$ etc). You may use it to validate different properties/specifications/behaviour of a design. Test benches can be designed around assertions to validate/verify the design. In VHDL, assert are non-synthesisable constructs, but you may keep ...

4

What tool do I use to ensure that all signals and variables used inside a process are assigned an initial value in the process, maybe when reset is asserted or maybe every clock cycle? Same as every other test: you write a testbench that checks for defined value.

4

Something like, using an array aggregate : a <= (1 => '0', 3 => '1', others => '0'); -- or simpler a <= (3 => '1', others => '0');

4

I have been programming in VHDL for 12 years, and I have never found the use of null to be a requirement. There may be some older tools out there that require it, but I have yet to come across one. null can be used to make your code more readable by explicitly stating that a certain condition doesn't do anything.

4

The target of a signal assignment statement can be an aggregate or a signal name (IEEE 1076-2008 10.5.2 Signal assignment) while x & y is an expression. You might benefit from perusing the standard or just the VHDL syntax (described in an Extended Backus Naur Form in the standard and useful VHDL books). Performing an aggregate assignment with objects of ...

3

Here is essentially what the hardware looks like. The i_ prefix means input or intermediate signal to a register. What you have is one register for detecting a falling edge on the Switch_1 signal and another register for toggling the LED output whenever a falling edge occurs on the Switch_1 signal. Note that wrapping the output of a register back to the ...

3

Your entity signals clk, load and reset should be of type std_logic. You cannot apply a rising_edge detection on a std_logic_vector. Further, the load signal doesn't have to be in your sensitivity list. The sensitivity list holds the signals that should cause a re-elaboration of your process but q is not elaborated when load changes but only on the rising ...

Only top voted, non community-wiki answers of a minimum length are eligible