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Assert 'must be power of 2' in VHDL?

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Matthias Schweikart's user avatar
1 vote

Assert 'must be power of 2' in VHDL?

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Matthias Schweikart's user avatar
2 votes

Encryption of Verilog/VHDL module

With IEEE-1735, private key is only needed for decrypting files. Anyone with the relevant public keys can encrypt its IP to target a specific tool. Synthesis/simulation tools vendors usually have a ...
Nipo's user avatar
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Packaging synthesized design as netlist for use in future designs

TL;DR Not possible in the free version of Quartus. The term you are looking for is exporting of "post-synthesis netlists". This generates a .qxp file for ...
Tom Carpenter's user avatar
1 vote

Adding VHDL DDR Memory Interface IP to block design in XIlinx Vivado

AXI4 is only available in verilog mode. And when you instantite MIG in IP Itegrator (IPI), AXI4 is by default enabled. And user cannot disable it. So you are forced to use verilog when using MIG in ...
Im Groot's user avatar
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Feedback in combinational digital circuits

Feedback in combinational circuits is discouraged due to timing issues. The example with the ACT-1 cell implementing an RS latch is specific to that component and might be designed to handle feedback. ...
samirjivani's user avatar
1 vote

Use VHDL to create a simulated EEPROM component for testbench

You can do this by using arrays of arrays: ...
Matthias Schweikart's user avatar

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