I've always been told that a signal updates its values after a wait
statement, or after a rising edge if we have for example 'if
You've been misinformed somewhat. In VHDL, a signal updates its value:
on a wait statement (not after it)
at the end of a process
On a wait statement means 'upon starting the wait statement'.
A process ...
A 'wait on' statement at the end of a process ensures that the process is carried out once at the start of simulation, before waiting for the signals it is sensitive to.
Superficially, a process with a sensitivity list is equivalent to a process with a a 'wait on' statement as its final line.
An important difference, though, is that a process with a ...