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Error (10500): VHDL syntax error at setpoint.vhd(37) near text "when"; expecting ";"

when - else construct is a concurrent statement in VHDL. You cannot use it inside a procedural construct like process (). It has to be described outside ...
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(others => '-') in VHDL

I am pretty sure it is because it doesn't make sense to assign a Don't Care. Don't Care is a umbrella grouping that represents multiple valid, but distinct, values so it only makes sense as a ...
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How to achieve signal gating with trigger input

You can achieve the pulse-gating in your requirement, using a negative level-sensitive latch and an AND gate. Modified version of typical Clock Gating cells found in ASIC libraries. If you describe ...
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1 vote

Synthesize of "REAL VARIABLES" in Vivado 2020.1

To determine whether a given construct is synthesisable in Vivado, you can refer to the Vivado Design Suite User Guide: Synthesis (UG901) document. This includes a full breakdown of which Verilog, ...
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1 vote

Vivado: Design failed to meet timing requirements. Is it because of ifs?

There is a simple mistake here: the XAUI block is clocked with a 10 MHz clock from a PLL (that is instantiated by the clock wizard), but the reset signal is ...
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How to implement do-while loop in VHDL?

While less compact than do-while, VHDL does contain the loop-...
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2 votes

How to implement do-while loop in VHDL?

You could use an infinite loop and exit at the end condition; that's the clearest way. Otherwise put the code in a function/procedure (if feasible) and call it once before the while and once inside ...
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2 votes

How to design interfaces for memory hungry circuits

You have an "external" memory interface either way. The array in VHDL is referenced by an index, and you pass the index you want to read or write through a ...
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Does VHDL allow a std_logic_vector port with no bounds?

This unconstrained declaration is valid, but it depends on another definition outside this module. Note that no "generic" declaration is required for this simple D Flip-Flop example: ...
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AXI master bus functional model in vhdl

In an AXI4 Manager (either RTL or a Verification component), you need a FIFO between the operation dispatch side (aka the user or transaction interface) that wants to do a read or write operation on ...
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How to apply two NOT gates sequentially in VHDL?

Well, what you want is some delay, not really NOT gates. What do you want that delay for? Adding random gates isn't a reliable solution, logic synthesis will optimize equations as needed. Depending on ...
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1 vote
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4 input multiplexer in VHDL

Repeat the lines: library IEEE; use IEEE.std_logic_1164.all; Like this (before the second entity): Which works when elaborating 'mux4':
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