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36

Vias in the pads are useful in high speed designs since they reduce trace length and therefore inductance (i.e. the connection goes straight from pad to plane rather than pad-trace-via-plane) You have to check whether your PCB house can do this though, and it may cost more (via will need to be plugged and plated over to provide a smooth surface) If you can't ...


31

Try not to fixate too much on the fact that these are vias in a PCB. The point is that they represent impedance changes in the signal's path. These effects are not unique to vias, they can be caused by many different signal path geometries. The titles under the graphs (on page 18, slide 36 of your linked PDF) tell which impedance change is most dominant for ...


25

Ok, first I am going to try to give a nice little primer on thermal engineering, since you say you want to get a better handle on it. It sounds like you're at that point where you understand the terms, have seen some of the math, but a true intuitive understanding has yet to develop, that 'Ah hah!' moment with the light bulb going off hasn't happened yet. ...


23

As an addition to Armandas' answer: If you want to use vias, there is a simple trick to swap the lines: Rotate the vias by 90 degrees, i.e. put them "above" each other. If you enter both vias from the left in the top layer and leave them to the left in the bottom layer, both lines are swapped at no expense: (Just a quick drawing as my schematics computer ...


22

I actually prefer vias as testpoints for just the reasons you mentioned. I think it makes using a multimeter or a scope probe much easier. Which, after all, is the main use of testpoints. Where possible/practical, I like to size my vias large enough or use small plated through holes so that 30 gauge wire can easily be soldered in. Then I can clip a scope ...


22

PCB production after stack up cure: Drill the hole. This is through the solid copper (un-etched) outer layers and feature etched internal layers (for a 4+ layer board). Copper burrs are removed in the deburring process. Melted epoxy resin is removed by a chemical desmear process. (Without this, you cannot get good plating coverage to the internal copper.) ...


19

Using a linear regulator where such a lot of power is dissipated is ill-advised. Your PCB is going to be like a heater. This means that from 5.52 watts of power only 1.15 will be useful power which brings you to 20.8 percent efficiency. Which is frighteningly low. Can you make efficiency higher? Yes, of course. If you used 110/230VAC source you could lower ...


18

"because it can cause problems during manufacturing" If right angle traces come loose you have to go to another PCB manufacturer. Quality PCBs don't have this problem anymore. On HF boards right angles are avoided because of radiation they cause (reference, p.14). Otherwise the only reason seems to be aesthetical. You can safely part from your via on ...


18

In general it's bad practice: the solder paste may get sucked in the via capillarily, leaving too little to solder the part's connection. I would place the via as close as possible next to the pad, with a narrow connection which won't draw the solder paste from the pad. There's a technique called tented via which avoids this by covering the top of the via, ...


17

I think the main problem is: vias could occupy significant space from other components, thus a larger board is necessary. On the first picture a TH vias allow us only four pads to be placed. But with a blind via or without a via we have place for six (or more if we have more rows) pads. A larger BGA component could be placed here this way. source And at ...


15

The goal is to create a via with at least as much conductive area within the hole as the trace connecting to it (generally speaking, of course). My personal rule is to make the drill size diameter the same as the width of the trace, and the pad size roughly twice the diameter. This gives you a little bit of leeway in case your board is too dense to allow ...


14

It sounds like these test points were thru hole pads, not necessarily vias. Yes, you can use a thru hole pad as a test point, especially if it is not intended for automated testing. For a technician, a thru hole pad can be convenient. A pad doesn't really add cost except for using space, it is easy to hold a scope probe on it, and you can solder a wire to ...


13

If those clearances are in spec for your shop, you're using a very advanced shop. The drill registration, in particular, must be very good. Normally, the pad around the via is just big enough so that if the drill hole is off center (to the limits of its tolerance), the hole won't break out more than x % of the perimeter of the pad. If that's what you're ...


13

There isn't one. That said, there are some thing I've gathered over time. What you do with the ground planes depends heavily on what you're trying to do. You could be trying to provide low impedance paths, or you could be trying to isolate one area from another, or you could be trying to deal with EMI. There certainly is a performance penalty for doing ...


13

I suggest you combine the two methods. Drill a hole near the traces and thread a thin bare wire through the board, lay it along the exposed traces by a few mm and solder it on both sides. If you don't have such a wire handy, just strip a piece of stranded wire and use one of the strands Nobody will notice unless they look very carefully, and it will be ...


13

You can set the default via through DXP->Preferences->PCB Editor->Defaults->Via For placing vias in interactive routing, you can press 4 and cycle through sizes of via- minimum, maximum, preferred or user choice (favorite). Shift-V during interactive routing allows you to select a favorite from a list- and you can customize the list through DXP->...


13

I wouldn't say that vias are bad. They are not! One useful way to use vias is to shield RF energy in a RF board, a technique called via stiching:


13

Having vias placed on a pad is common practice. Nevertheless there are disadvantages which makes designers place vias next to a pad, in some cases even by removing some pads from the BGA footprint. If there is a via in pad, it needs to be filled, either galvanically with copper or with some kind of non-conductive material and then covered in copper. An open ...


13

Do you see any further things I could optimize? Without giving it too much thought, about 10 11 12 13 came to mind. Thermal Pad Area Junction to Case Thermal Resistance Thin PCB Copper or Silver Filled Vias Thermal Epoxy MCPCB Thermal Encapsulants Bare Copper Heat Spreader Planes Case Emissivity Vent Holes Orientation Switcher It looks like you may be ...


12

Complexity Levels (or Class levels) There are several factors that contribute to the complexity of a castellated hole. The main critical design attributes are: Hole size Number of holes per board Single hole or multiple hole designs Surface finish Recommendations and comments When castellated features are required, it is best to use the following ...


12

You're actually talking about two very different things. One, via stitching, is the grid-like pattern of vias you might see connecting two ground planes. The other, via fences, are vias that completely surround an RF trace on all sides, save maybe for the end terminating to an antenna or similar. Now, it is a good idea to stitch ground planes together ...


11

I'd love to say there is a simple answer, but there is not, there are too many variables However you can break the problem down..... The sizes you select mostly depend on what the capabilities of the fab you are using. For low cost, reliability, and high yield choose the largest vias and largest traces you can, while keeping annular rings as large as ...


11

Yes, one of the reasons for using 2-layer PCBs is to avoid the jump wires. On a complex board there would be lots of them in all directions. Your layout doesn't need the second layer, though; it's still simple enough to be routed on a single layer without wire bridges. If you get stuck you may have to move some components to another position, but it can be ...


11

There are some awful QFN packages (DQFN) with two rows of pads where you absolutely have to do this, so I can confirm that it is possible. @The Photon covered all of the dangers of doing this better than I could. This application note has some good general guidelines. For reference, here's a picture the DQFN-124 that I'm working with right now: The only ...


11

VIA in trace is OK unless you are designed for high speed signals or very high current. The change in impedance and capacitance can cause signal integrity issues, reflections, for high speed signals. Also keep in mind if the trace is carrying a lot of current, as the size of the "donut" can affect the amount of current flow (resistance change, temperature ...


11

It is just one of the parameters you can use to tweak the autorouter. Via's add a little cost in drilling (even though this might not be explicitly shown on the bill), they take up space, and other things being equal it is better for a route to stay on the same layer. I can imagine (but I am not sure) that a via is just a little bit less reliable than a ...


10

SPI bus at 50MHz can easily run a couple of inches thru a few vias without hitch. Wavelength of 50MHz is 6 metres but realistically because fast edges are used you need to think ten times faster. Even so that's a wavelength of 60 cm. Rule of thumb is keep tracks smaller than a half of a quarter wavelength (other folk will use other rules of course) and this ...


10

Well, I spent a solid hour or so trying to find the answer, gave up and asked here. Then a few minutes later I had the idea of seeing what shortcuts are available during routing (Ctrl-F1) and then finding that the 5 key will go through via patterns, one of which is the pattern I was looking for. So, pressing 5 while routing multiple net's will give you ...


10

When you're setting up a new PCB rule, you can type "query text" to match objects to which the rule should apply. When I do what you're trying to do, I just use "isVia" as the query text and then set the Connect Style to Direct Connect: I'm not sure how to exclude your QFN's thermal stitching vias though...


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