# Tag Info

19

Triplication means (as noted) to make 3 of everything. It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the erroneous result circuit is reset. For this to work within a single device, partial reconfiguration in the FPGA is required. The reason this is necessary in SRAM ...

6

The FPGA configuration itself is stored in SRAM (i.e. flip-flops). A newly started FPGA has an empty configuration where typically all pins are in a somewhat idle state (e.g. weak pull-up), and clocks are not forwarded inside the FPGA, so no activity takes place. From that state, either the FPGA boots actively by accessing an external device (usually, flash ...

4

No, you have misunderstood the concept of "aspect ratio". Each chip has a fixed number of block RAMs in it; you can find this number in the datasheet. Each of those block RAMs holds 18K bits, and can be configured to access those bits in a number of different ways, from 16K words of 1 bit each, to 512 words of 36 bits each. In the first case, you can read ...

3

There are several possibilities: You can use ChipScope. That's an on-chip logic anaslyzer, which is synthesized into your design. You can implement (or use) a FPGA to PC communication like UART to write numbers and read results. You can implement a testcase in hardware (like your testbench) that enlights a LED if the testcase is passed. ...

3

I presume you are using the WebPack edition? In which case no, it is not supported. You need to use the ISE Design Suite version to support the Virtex 5 LX110. This requires you to purchase a software license.

3

So I think I found some answers to the problem and want to share them. I started to simulate the GTXE2_CHANNEL hardmacro. The simulation is behaving as "false" as the hardware. So I tried to simulate the MGT in Verilog and used an instance template from here: http://forums.xilinx.com/t5/7-Series-FPGAs/Using-v7gtx-as-sata-host-PHY-and-there-is-issue-bout-...

3

Wow, using a Virtex-5 for this is massive overkill - on the scale of using a nuke to open a peanut. I'm not sure what voltage the I/O on the Genesys board runs at; as long as it's 3.3V (and it probably is) you should be able to connect a LED of any colour via a series resistor (higher or lower value for lower or higher brightness, start with 1kohm) to ...

3

Xilinx has been inconsistent with the LVDS iostandard, I won't delve into earlier generations than spartan-6! First, LVDS is current based (3.5mA into 100 ohm, around 350mV swing) and is electrically the same whatever the bank voltage. Spartan-6 supports LVDS outputs from a bank with a VCCO of 3.3 (LVDS_33) or 2.5 (LVDS_25). Since Virtex-6 doesn't support ...

2

Physical layer Are the 64 GPIOs all you have or do you have any other connections between the FPGAs? As indicated by Martin Thompson, for bandwidth you'd be better off using high speed serial connections if available. Assuming your original post contains all the relevant data and you only have 64 GPIOs then you'll need to think about how you're going to ...

2

As it's Xilinx, you could look at using Aurora to interface between the FPGAs - you'd have to implement your own memory access protocol over the top of it, but it allows you to easily get very high bandwidth between chips using the inbuilt SerDes (GTP) pins. It will handle all the lane matching and channel bonding and save you from the pain of trying to ...

2

Implement a DDR controller on FPGA B. Attach the DDR controller to a shared memory interface controller. Attach shared memory interface bus A to FPGA B internals. Attach shared memory interface bus B to FPGA B I/O pins. You may need to make some compromises, of course - 32 bits for data, 31 bits for address, 1 control line probably isn't going to work; you ...

2

You need several HardIPs for: PCIe bridges PCIe Switches custom designs that use PCIe as a board-to-board communication ... Common cores support up to 8 lanes and Gen2. More lanes are possible but need a Soft-IPCore. Also Gen3 is mostly provided as a Soft-IPCore.

2

SystemVerilog is a hardware description and verification language that has hooks into the host operating system that runs the simulation. None of these hooks are available to you in the actual hardware. However, if you are running your FPGA on a development board, then there may be hooks that the FPGA vendor provided to dump you memories to a file.

2

I thought again about your inversion problem. The problem is that you or your PCB or your device swapped the RX+ and RX- wires for the transceiver input. Your GTXE2 is configured to a 20-bit bus and no 8B/10B encoding, so the direct inversion of each bit seen in your measurement is caused by the wrong polarity at the input pins. You can enable polarity ...

2

I finally solved my problem and I post my answer here for futur generations. Consistently to the advice of Brian Drummond, I created a small testbench for each module of my system and I ran the synthesis as well as the post-synthesis simulation on each on of them. Everything was working fine, none of the synthesis were taking an excessive amount of time. ...

2

I believe this is due to the fact that the LUTs on the Spartan 6 are internally constructed as a 5 input, 2 output LUT followed by a bypassable mux. Now, why you can't make a 2 bit wide, 32 bit long shift register in a single LUT is a good question. Seems like that should be possible, and then it should be possible to loop the output of one side back around ...

2

If we assume 2 bytes per sample point (16 bits), then you have about 5 MB of database data, which pretty much dictates external memory to hold it on all but the very largest of FPGAs. The external memory interface will be the rate-limiting step in the correlation process. If you have a number of DDR memory chips you could have an interface that's, say, 64 ...

1

DSP48E1 slice in 7-series Xilinx FPGAs contains a 25x18 multiplier. You can make use of those DSP slices in your FPGA to implement bigger multipliers. Following simple behavioral code inferred me a 48x48 multiplier using DSP slices on Virtex-7, when synthesised in Vivado. Vivado synthesiser is smart enough to map the logic automatically to DSP slices, ...

1

According to the datasheet, page 6, which is always a good reading. The requirements for the $R_{SET}$ are: Power rating 0.05 W Tolerance 1% Temperature stability 100ppm/°C Also there information about the correct placement too.

1

Pins D15 and D18 are connected to the DDR3 memory. I presume you read the table wrong in the manual as those are the pin names on the FMC connector itself, so try G39 for ps2d and P42 for ps2c. Edit: try making ps2d and ps2c input instead of inout in the ps2 rx module. Better idea would be to replace each pin with three - input, output, and tristate/oe ...

1

You can check in the .mhs file that is created by EDK. In this file you will find a clock generator. Trace the input and output of this clock generator to know which IP runs at which frequency.

1

Without knowing more about your application, it's pretty clear that the problem is in MATLAB, not the PC. From your description, your processing algorithm is horribly inefficient, and a software rethink may save you a lot of time, effort, and money. Consider a Spearman Correlation. Instead of correlating 2 data arrays, x() and y(), it performs the ...

1

Take a look at Xilinx UG200 and the MPLB interface. This looks like the port that you will need to connect your memory mapped peripherals to, probably with a decent amount of interface logic.

1

Most synthesis tools don't support read/write support. Some of them report the usage of such functions as an error, others ignore such statement or even don't implement Std.TextIO. Xilinx ISE supports read/write in VHDL (I have not tested Verilog). Xilinx Vivado has some issues with file i/o. Contrary common consensus, there a good usecases for file i/o at ...

1

I don't have an answer, as I don't know the internal details of Xilinx slices. I do have some pointers. First, you can't save data in a LUT6. You can only save data in registers (which are numbered 2/LUT6) and distributed RAM/blockRAM. Which somewhat annul your LUT6 = 64 bits assumption. Distributed RAM and shift registers are somewhat unrelated to LUT6 ...

1

No, obviously not - how could it? None of the \$ extensions do.

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The problem to the question raised by me was actually an error in the connection of the output port in my case [can also be any i/o port] Thus in the instantiated module there was a connection made by wire using verilog coding in the top level file but in the module itself that output was not assigned any value. And since these outputs were supposed to be ...

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Make a vhdl component that halts MicroBlaze until it is finished counting to whatever size the DDR3 memory is, and each count it fills the area with either a (others=>'0') or a (others=>'1') to fill that byte, word, or quad of memory. hope this helps..

1

Currently I'm not allowed to write my questions as a comment ... so I'll write it as an answer and try to develop a solution. Have you checked if the PHY is receiving your TX clock? Have you connected ChipScope to the I/O flip flops incl. valid and error bits? If not, please capture all outgoing data to the PHY? Is your PC with WireShark directly connected ...

1

If you cannot connect the FPGA A to its own bank of memory, then I would venture to say that the 400 MHz GPIO lines between the two are your best bet. Using them in basic SPI configuration or something. If the board is routed properly, you could attempt to do some sort of PCIe communication between the two but that is very circumstantial. You could ...

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