19 votes

what is triplication on fpga?

Triplication means (as noted) to make 3 of everything. It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the ...
Peter Smith's user avatar
  • 22.2k
3 votes

Is there support XC5VLX110 list in ISE Project setting?

I presume you are using the WebPack edition? In which case no, it is not supported. You need to use the ISE Design Suite version to support the Virtex 5 LX110. This requires you to purchase a ...
Tom Carpenter's user avatar
2 votes

Why SATA ALIGN primitive is shifted or swapped on 7-Series GTXE2 transceiver RXDATA output?

I thought again about your inversion problem. The problem is that you or your PCB or your device swapped the RX+ and RX- wires for the transceiver input. Your GTXE2 is configured to a 20-bit bus and ...
Paebbels's user avatar
  • 3,907
2 votes

Why has a LUT6 based SRL only 32 entries but not 64?

I believe this is due to the fact that the LUTs on the Spartan 6 are internally constructed as a 5 input, 2 output LUT followed by a bypassable mux. Now, why you can't make a 2 bit wide, 32 bit long ...
alex.forencich's user avatar
2 votes

Timing complexity for correlation implementation on FPGA

If we assume 2 bytes per sample point (16 bits), then you have about 5 MB of database data, which pretty much dictates external memory to hold it on all but the very largest of FPGAs. The external ...
Dave Tweed's user avatar
  • 172k
1 vote

How to change the FPGA supply voltage (VCCint and VCCBRAM) beyond recommended operating conditions on Vivado?

The FPGA I am using is Virtex-7 VC707 -2 speed grade However, VC707 isn't the part number of a Virtex-7 but rather an evaluation kit - AMD Virtex 7 FPGA VC707 ...
Chester Gillon's user avatar
1 vote

How to implement a 48x48 multiplier using DSP48E slices in Verilog HDL?

DSP48E1 slice in 7-series Xilinx FPGAs contains a 25x18 multiplier. You can make use of those DSP slices in your FPGA to implement bigger multipliers. Following simple behavioral code inferred me a ...
Mitu Raj's user avatar
  • 10.9k
1 vote

what kind of type resistor do I need in PTH05050W?

According to the datasheet, page 6, which is always a good reading. The requirements for the \$ R_{SET} \$ are: Power rating 0.05 W Tolerance 1% Temperature stability 100ppm/°C Also there ...
Bence Kaulics's user avatar
1 vote

VC707 Eval Board - Synthesis/DRC issues during implementaion of a Microblaze Based PS2 Controller

Pins D15 and D18 are connected to the DDR3 memory. I presume you read the table wrong in the manual as those are the pin names on the FMC connector itself, so try G39 for ps2d and P42 for ps2c. ...
alex.forencich's user avatar
1 vote

How to find the clock speed my fpga runs in XPS or EDK?

You can check in the .mhs file that is created by EDK. In this file you will find a clock generator. Trace the input and output of this clock generator to know which IP runs at which frequency.
samjay's user avatar
  • 66
1 vote

How to interface UART with BRAM in xilinx virtex 5

Based on your second screen capture you are reading at addressb=1 NOT addressb=0. RdB gets set high in the "reading" state and addressb gets incremented, but these values do not get read out of the ...
ks0ze's user avatar
  • 522
1 vote

Timing complexity for correlation implementation on FPGA

Without knowing more about your application, it's pretty clear that the problem is in MATLAB, not the PC. From your description, your processing algorithm is horribly inefficient, and a software ...
WhatRoughBeast's user avatar
1 vote

Instantiating and using ppc440 core in Virtex 5 FPGA

Take a look at Xilinx UG200 and the MPLB interface. This looks like the port that you will need to connect your memory mapped peripherals to, probably with a decent amount of interface logic.
alex.forencich's user avatar
1 vote

Xilinx ISE Synthesis taking too long

I think You may using 32 navigator on 64-bit system. Just recompile it on 64 project navigator. It makes much difference.
Harsha's user avatar
  • 11

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