Hot answers tagged

12

Has the placer violated space constraints? No. Has the router violated timings constraints? Probably not, if it finished successfully. In which case you have a good design. If you reduced the size of chip available to it, you'd find it would put more latches per slice. If you tightened the timing constraints, you might find that if local routing ...


10

If it is removing them, they are in fact unused, but it is not always obvious why. I think in your case, the reason is: .sample_in({8{sw}}), The synthesiser is clever enough to realise the bits in each word of your memories (smp_buf and vga_buf) are identical. As a result, it decides there is no point duplicating the hardware, it might as well just have a ...


9

A bus enables you to define values that are wider than one bit. If you want to store or transmit (in parallel) a value between 0 and 15, you need a 4-bit bus. An array lets you store multiple values under a single name. The difference between "[7:0] data" and "data[7:0]" is that the first is a single 8-bit-wide value while the second is eight single-bit ...


6

My personal workflow (I mention planAhead, but vivado is similar), with goal to add as little as possible to source-control: Files exist outside the planAhead project directory. Take care since if you use the GUI to add/create files, it will likely be inside the project directory. IP cores exists in my source directories, one sub-folder by IP core. Every ...


6

Yes, it is legal SystemVerilog. Refer to IEEE Std 1800-2012 § 10.9 Assignment patterns my_struct s = '{default:'1, c:0}; is equivalent to my_struct s = '{a:16'hFFFF, b:16'hFFFF, c:16'h0000}; my_struct s = '{default:0, c:'1}; is equivalent to my_struct s = '{a:16'h0000, b:16'h0000, c:16'hFFFF}; Your version Vivado might not have implemented the default:...


5

Width of buffer length n: This is exactly what you think, the largest transfer in byte the IP can perform with a single command. 18 bits may be enough, but it's likely you need 19 bits to represent 2^18, check the datasheet to make sure. Memory Map Data Width This is on the AXI side. You can put what you want (AXI will upsize/convert as needed), but in my ...


5

You assign constant values to your VGA color lines, which will not work. An analog VGA monitor expects to see a reference "black" level during part of the off-screen duration of the trace. If you drive a substantially non-zero value there, it will adapt to the idea that this voltage means black, and you will not get the expected rectangle of color (on some ...


5

Vivado is Xilinx's next-generation replacement for ISE. It was released in 2012, and since 2013 there have been no new versions of ISE. You have to use Vivado if you're working with the 7-series FPGAs* or newer. However, Vivado cannot target older FPGAs including the Virtex 5, so you're stuck with ISE for those. * (with some limited exceptions - ISE can ...


5

When your program makes the synthesis of your VHDL, plenty of reports are generated. Normally you can see detailed logic resources usage per VHDL block, component and so on. This is the way I do it in Quartus.


4

It's recommened to use clock capable pins (CC Pins) for clock inputs. These can be routed to BUFGs. But the error it in another part of your code. As you wrote you are using if rising_edge(input) then You cannot use rising_edge on none clock nets, this promotes them to a clock net, which input isn't. The correct way is to synchronize the input with 2 D-...


4

Just write one. It's only a few lines of VHDL. Depth can be a generic natural, and it can take its width from the ports. Synth it independently and check that ISE/Vivado use the expected shift register mode in LUTs. If you can't easily wrap it as a block, that calls the usefulness of the whole block diagram approach into question. Most of these things go ...


4

Are they broken all the way out to your top-level design? If not, you have to define some external ports in your block diagram, and then assign them in your constraints (XDC) file. Otherwise, those pins will remain internal / not-connected. Right-click in the BD, and create a port (Ctrl+K): Then, when you auto-generate the wrapper for the block diagram, ...


4

In all likelihood, yes, the inout will be optimised away. In fact in almost all devices there are no internal tri-state buffers on routing, so inout ports usually get converted into a series of multiplexers. If you have an inout port always being driven inside a module, then the logic will simplify down. However, if you connect two inout ports together, ...


4

Use the type system instead of fighting it. Any time you see an uncomfortable double type conversion, especially to another type and immediately back again, like temp := std_logic_vector(unsigned(temp) + 1); that is fighting the type system, and probably points to a more or less serious mistake in the design. Instead, think about this: You want to ...


4

You have problems with the Operator Precedence. The comparison ( < ) has higher precedence then you EXOR operator ( ^ ). Thus first j < 2 is calculated as true (1) or false (0). Then that is EXOR-ed with 7, which gives either 6 or 7. But it never gives 0 (false) so the loop does not finish. Try: j < (2^(N-1)) or what you probably want: j < (1&...


4

Don't add the project itself to git; instead add some sort of script to generate the project and required IP cores. There are all sorts of issues you'll run in to if you commit the actual project, the least of which being absolute paths in various places, not to mention a hard version dependence on Vivado. It should be possible to have Vivado export a TCL ...


4

TL;DR; The answer may depend on the synthesis tools, but most likely the answer is no unless you use randomised seeds. Certainly for modern versions of Intel/Altera Quartus (since some time before 12.1), if you compile the exact same source files using the exact same software version (including subversion/patch level) for the same device, you will get the ...


4

Unconstrain the output (set a false path) and the timing violation will go away. In Vivado you put these in the .xdc file for your design. More about that here: https://forums.xilinx.com/t5/Timing-Analysis/What-does-quot-set-false-path-through-quot-do/td-p/397531 set_false_path is part of the group of tcl commands called SDC, short for Synopsys Design ...


3

It's exactly as the warning says, you are mixing synchronous logic with asynchronous logic. You can not use ... or posedge start ....


3

Using a generic VHDL code snippet is much smaller.... Example: PoC.mem.ocrom.tdp entity ocram_tdp is generic ( A_BITS : positive; D_BITS : positive ); port ( clk1 : in std_logic; clk2 : in std_logic; ce1 : in std_logic; ce2 : in std_logic; we1 : in std_logic; ...


3

Looking at these two lines: shiftout : out std_logic_vector(1 downto 0) and shiftout <= shiftreg(31); The first declares shiftout as being two bits wide. The second tries to assign to this a one-bit value. Your two options are: Redfine shiftout to be one bit wide: shiftout : out std_logic or change the assignment to match the output width: ...


3

There is nothing in the SystemVerilog language that allows you to specify outputs that are allowed to be left unconnected. And you don't want to globally turn off dead code removal warnings because that could mask much larger problems. I see three possible choices: Write a script that filters your messages to eliminate the warnings from the dead logic that ...


3

Xilinx Vivado: You can create/change the library a file resides in Vivado by clicking on the file, then clicking the button to the right of the Library label in the Source File Properties tab. You can create a library by assigning a file to a library that doesn't exist. Altera Quartus II: You can specify the library under Properties, for example: ...


3

Simple answer. No, I don't think it is. There is a very useful online reference/help document which has pages describing Verilog constructs and syntax. It has a page on the $realtobits function, which state Conversion functions are not synthesizable. I can't vouch for the accuracy of the source, but it makes sense. The Verilog $... functions tend to be ...


3

In VHDL you cannot use arithmetic operators with std_logic_vector. The problem is that the compiler don't know whether you want to use a signed or unsigned vector. To avoid this, you can declare your signals as singed/unsigned or just convert them when you want to multiply them using unsigned(your_slv)or signed(your_slv).


3

If I told you, I'd have to shoot you ... For whatever reason, that kind of information is a closely-held secret among the developers of the Vivado GUI environment, which saves all kinds of files for its own purposes — presumably to save time by avoiding the execution of process steps that don't need to be repeated. Unfortunately, it is so bad at ...


3

Vivado HLS lets you generate code in a hardware description language from a high level language, for example C or C++. SDSoC can be seen as Vivado HLS with etra functionality, e.g., the possibility to combine the developed hardware with a Zynq and Linux running on the ARM cores. Furthermore, it offer additional analysis opportunities, for example to improve ...


3

The problem with your code is that an assignment of the form: a <= (3 => '0', others => '1'); must use constants for the offsets being assigned (in this case, 3). If you need the offset being set to vary, you have to split it into two assignments. Note that this will only work inside a process; with a pair of concurrent assignments, you would ...


3

Since this was originally posted I have ditched this ADI-based design for one based off the TRD. For anyone with a similar problem, I found a correct build of the ADI reference design here (same as Steven's link but his was broken for me), and it requires custom drivers found here. But it is worth noting that I switched my approach because the ADI design ...


3

This : assign clk = (freq_val=='d0) ? clk_5M : (freq_val=='d1) ? clk_10M : clk_200M is dangerous. And wrong as you can't get clk_200M out of that but I assume that is just a typo You must make sure that you do not generate 'runt' clock pulses. (Clock pulses which are too short high or low). If all those clocks are synchronous and have coinciding rising ...


Only top voted, non community-wiki answers of a minimum length are eligible