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Why is vivado so wasteful with its D-flipflop placement?

Has the placer violated space constraints? No. Has the router violated timings constraints? Probably not, if it finished successfully. In which case you have a good design. If you reduced the size ...
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10 votes
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Vivado is removing registers which will be used

If it is removing them, they are in fact unused, but it is not always obvious why. I think in your case, the reason is: .sample_in({8{sw}}), The synthesiser is ...
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10 votes
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What is the difference between an array and a bus in Verilog?

A bus enables you to define values that are wider than one bit. If you want to store or transmit (in parallel) a value between 0 and 15, you need a 4-bit bus. An array lets you store multiple values ...
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10 votes
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Clock Phase Shift Not Working on FPGA

When there is a 90° phase shift between two 5MHz clocks, that means there is a 50ns skew between them. If you divide those two clocks by 5000000 using two instances of the same counter structure, you'...
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7 votes
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systemverilog structure initialization with default = '1

Yes, it is legal SystemVerilog. Refer to IEEE Std 1800-2012 § 10.9 Assignment patterns my_struct s = '{default:'1, c:0}; is equivalent to ...
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6 votes
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Which is the best way to version control Xilinx PlanAhead projects?

My personal workflow (I mention planAhead, but vivado is similar), with goal to add as little as possible to source-control: Files exist outside the planAhead project directory. Take care since if ...
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6 votes

Implement glDrawArrays function in FPGA

This question shows a fundamental lack of understanding about how all these things relate, and is therefore unanswerable, except to explain why the question doesn't make sense. It's like you asked: I ...
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6 votes
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How to declare a global variable in Verilog

You are asking the wrong question. In Verilog simulation, every signal can be a global. For debugging, we need to be able to see and potentially modify everything. In Verilog synthesis, nothing is a ...
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6 votes

Vivado Simulation Running Very Slow

Welcome to the wonderful world of FPGA simulation. Yes, simulations take a long time. Running for a full second is a lot of simulation. One trick you can do is speed up your blink rate just for the ...
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5 votes
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Axi DMA correct parameters

Width of buffer length n: This is exactly what you think, the largest transfer in byte the IP can perform with a single command. 18 bits may be enough, but it's likely you need 19 bits to represent 2^...
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5 votes

VGA driver not working

You assign constant values to your VGA color lines, which will not work. An analog VGA monitor expects to see a reference "black" level during part of the off-screen duration of the trace. If you ...
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5 votes
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what is the difference between ISE and Vivado?

Vivado is Xilinx's next-generation replacement for ISE. It was released in 2012, and since 2013 there have been no new versions of ISE. You have to use Vivado if you're working with the 7-series ...
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5 votes
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Is it possible to see how much logic an IP core uses?

When your program makes the synthesis of your VHDL, plenty of reports are generated. Normally you can see detailed logic resources usage per VHDL block, component and so on. This is the way I do it in ...
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5 votes

Vivado Simulation Running Very Slow

F = 200 MHz or T = 5 ns is the fastest clock in your design and it looks like you don't have any events in your design to be captured at 100 ps precision. You can run simulation with a precision of ...
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4 votes

How to solve routing issues in Artix7?

It's recommened to use clock capable pins (CC Pins) for clock inputs. These can be routed to BUFGs. But the error it in another part of your code. As you wrote you are using ...
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  • 3,807
4 votes

Xilinx IP for delaying data

Just write one. It's only a few lines of VHDL. Depth can be a generic natural, and it can take its width from the ports. Synth it independently and check that ISE/Vivado use the expected shift ...
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4 votes
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found '0' definitions of operator "*"

In VHDL you cannot use arithmetic operators with std_logic_vector. The problem is that the compiler don't know whether you want to use a signed or unsigned vector. ...
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4 votes
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How to map custom IP to the output pin on FPGA

Are they broken all the way out to your top-level design? If not, you have to define some external ports in your block diagram, and then assign them in your constraints (XDC) file. Otherwise, those ...
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4 votes
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Will inout ports used only as in or out be optimized?

In all likelihood, yes, the inout will be optimised away. In fact in almost all devices there are no internal tri-state buffers on routing, so ...
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4 votes

Error while simulating vhdl code for 4 bit counter in vivado 2015.2

Use the type system instead of fighting it. Any time you see an uncomfortable double type conversion, especially to another type and immediately back again, like ...
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4 votes
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VHDL: Demultiplexing a signal to one of many outputs while driving unused outputs to '0'

The problem with your code is that an assignment of the form: a <= (3 => '0', others => '1'); must use constants for the offsets being assigned (in this ...
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  • 1,937
4 votes
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how to pass parameter variable to module in verilog

Parameters are defined at synthesis time, you can't change them at run time based on signals. With that in mind, there are basically two options: either convert that parameter to a signal, or ...
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4 votes
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Verilog nested for loop not behaving as expected

You have problems with the Operator Precedence. The comparison ( < ) has higher precedence then you EXOR operator ( ^ ). ...
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4 votes

How are Vivado's projects directories structured?

Don't add the project itself to git; instead add some sort of script to generate the project and required IP cores. There are all sorts of issues you'll run in to if you commit the actual project, the ...
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4 votes
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Inherent Pseudo-Randomness in modern FPGA design tools

TL;DR; The answer may depend on the synthesis tools, but most likely the answer is no unless you use randomised seeds. Certainly for modern versions of Intel/Altera Quartus (since some time before 12....
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4 votes
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Passing input on one pin of FPGA straight out to another output pin for monitoring

Unconstrain the output (set a false path) and the timing violation will go away. In Vivado you put these in the .xdc file for your design. More about that here: https://forums.xilinx.com/t5/Timing-...
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4 votes

VHDL Synthesis Warnings

As BrianDrummond pointed out in the comment section, I was driving the same pins in my source file multiple times. Although this is only in simulation as it is during the test phase, and not on a FPGA ...
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4 votes
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wrong output of a multiplier in IP catalogue

The value of 0xFFF on the output is correct. Multiplying 0x001 and 0xFF6 as 12 Bit signed integers results in 0xFFFFF6. Now you specify the output width as 12 Bit - and the uppermost 12 Bit of the ...
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3 votes
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Why do I get a "[Synth 8-5413] Mix of synchronous and asynchronous control for register" warning in Vivado?

It's exactly as the warning says, you are mixing synchronous logic with asynchronous logic. You can not use ... or posedge start ....
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  • 3,807
3 votes
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Artix 7 Block RAM instantiation in Vivado 2015.2

Using a generic VHDL code snippet is much smaller.... Example: PoC.mem.ocrom.tdp ...
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