12 votes
Accepted

What is the difference between an array and a bus in Verilog?

A bus enables you to define values that are wider than one bit. If you want to store or transmit (in parallel) a value between 0 and 15, you need a 4-bit bus. An array lets you store multiple values ...
Willis Blackburn's user avatar
12 votes
Accepted

Why is vivado so wasteful with its D-flipflop placement?

Has the placer violated space constraints? No. Has the router violated timings constraints? Probably not, if it finished successfully. In which case you have a good design. If you reduced the size ...
Neil_UK's user avatar
  • 166k
10 votes
Accepted

Clock Phase Shift Not Working on FPGA

When there is a 90° phase shift between two 5MHz clocks, that means there is a 50ns skew between them. If you divide those two clocks by 5000000 using two instances of the same counter structure, you'...
Nipo's user avatar
  • 1,628
9 votes

FPGA logic threshold - distinguishing a logic 0 and 1

The logic levels are shown in Table 8 of your referenced datasheet.
jonathanjo's user avatar
7 votes
Accepted

How to declare a global variable in Verilog

You are asking the wrong question. In Verilog simulation, every signal can be a global. For debugging, we need to be able to see and potentially modify everything. In Verilog synthesis, nothing is a ...
dave_59's user avatar
  • 8,357
7 votes
Accepted

Vivado constraints wizard suggests a lot of nonsense generated clocks

The following code in alu infers a latch: ...
toolic's user avatar
  • 8,332
6 votes

How are Vivado's projects directories structured?

Don't add the project itself to git; instead add some sort of script to generate the project and required IP cores. There are all sorts of issues you'll run in to if you commit the actual project, the ...
alex.forencich's user avatar
6 votes

Implement glDrawArrays function in FPGA

This question shows a fundamental lack of understanding about how all these things relate, and is therefore unanswerable, except to explain why the question doesn't make sense. It's like you asked: I ...
user253751's user avatar
  • 12.5k
6 votes

Vivado Simulation Running Very Slow

Welcome to the wonderful world of FPGA simulation. Yes, simulations take a long time. Running for a full second is a lot of simulation. One trick you can do is speed up your blink rate just for the ...
td127's user avatar
  • 3,077
6 votes
Accepted

Will FPGA synthesis tools ignore unused modules?

Unlike software where the compiler will sometimes keep code around that isn't actually called (particularly for things like libraries), this isn't the case for HDL designs. This is because HDL isn't &...
alex.forencich's user avatar
5 votes

VGA driver not working

You assign constant values to your VGA color lines, which will not work. An analog VGA monitor expects to see a reference "black" level during part of the off-screen duration of the trace. If you ...
Chris Stratton's user avatar
5 votes
Accepted

Is it possible to see how much logic an IP core uses?

When your program makes the synthesis of your VHDL, plenty of reports are generated. Normally you can see detailed logic resources usage per VHDL block, component and so on. This is the way I do it in ...
Cristian Mardones's user avatar
5 votes
Accepted

what is the difference between ISE and Vivado?

Vivado is Xilinx's next-generation replacement for ISE. It was released in 2012, and since 2013 there have been no new versions of ISE. You have to use Vivado if you're working with the 7-series ...
pericynthion's user avatar
  • 6,174
5 votes

Vivado Simulation Running Very Slow

F = 200 MHz or T = 5 ns is the fastest clock in your design and it looks like you don't have any events in your design to be captured at 100 ps precision. You can run simulation with a precision of ...
Mitu Raj's user avatar
  • 10.9k
5 votes

Multiplication in VHDL by a fraction

In the testbench, there are numerous values listed for same simulated time. From the language reference: The delay values supported with the after clause do not cumulate, but all relate to the same ...
greybeard's user avatar
  • 1,811
5 votes

What are the multiple drivers in this code?

You make assignments to count from 2 different always blocks. You must only make assignments to a signal from one ...
toolic's user avatar
  • 8,332
4 votes
Accepted

found '0' definitions of operator "*"

In VHDL you cannot use arithmetic operators with std_logic_vector. The problem is that the compiler don't know whether you want to use a signed or unsigned vector. ...
A. Kieffer's user avatar
4 votes
Accepted

Will inout ports used only as in or out be optimized?

In all likelihood, yes, the inout will be optimised away. In fact in almost all devices there are no internal tri-state buffers on routing, so ...
Tom Carpenter's user avatar
4 votes
Accepted

How to map custom IP to the output pin on FPGA

Are they broken all the way out to your top-level design? If not, you have to define some external ports in your block diagram, and then assign them in your constraints (XDC) file. Otherwise, those ...
Krunal Desai's user avatar
  • 6,306
4 votes
Accepted

VHDL: Demultiplexing a signal to one of many outputs while driving unused outputs to '0'

The problem with your code is that an assignment of the form: a <= (3 => '0', others => '1'); must use constants for the offsets being assigned (in this ...
scary_jeff's user avatar
  • 1,987
4 votes
Accepted

how to pass parameter variable to module in verilog

Parameters are defined at synthesis time, you can't change them at run time based on signals. With that in mind, there are basically two options: either convert that parameter to a signal, or ...
alex.forencich's user avatar
4 votes
Accepted

Verilog nested for loop not behaving as expected

You have problems with the Operator Precedence. The comparison ( < ) has higher precedence then you EXOR operator ( ^ ). ...
Oldfart's user avatar
  • 14.4k
4 votes
Accepted

Inherent Pseudo-Randomness in modern FPGA design tools

TL;DR; The answer may depend on the synthesis tools, but most likely the answer is no unless you use randomised seeds. Certainly for modern versions of Intel/Altera Quartus (since some time before 12....
Tom Carpenter's user avatar
4 votes
Accepted

Passing input on one pin of FPGA straight out to another output pin for monitoring

Unconstrain the output (set a false path) and the timing violation will go away. In Vivado you put these in the .xdc file for your design. More about that here: https://forums.xilinx.com/t5/Timing-...
hacktastical's user avatar
  • 54.1k
4 votes

VHDL Synthesis Warnings

As BrianDrummond pointed out in the comment section, I was driving the same pins in my source file multiple times. Although this is only in simulation as it is during the test phase, and not on a FPGA ...
David777's user avatar
  • 1,578
4 votes
Accepted

wrong output of a multiplier in IP catalogue

The value of 0xFFF on the output is correct. Multiplying 0x001 and 0xFF6 as 12 Bit signed integers results in 0xFFFFF6. Now you specify the output width as 12 Bit - and the uppermost 12 Bit of the ...
asdfex's user avatar
  • 2,729
4 votes

Will FPGA synthesis tools ignore unused modules?

Vivado has a specific property top that you can use to set the top-level module. From there, the elaboration process looks recursively down the hierarchy collecting ...
dave_59's user avatar
  • 8,357
4 votes
Accepted

How to transfer Vivado projects properly between PCs?

Today we tried a lot and found some ways to fix it. First of all it seems like it occurs because Vivado tries to delete or overwrite old synthesis Data, which it could not be located because the paths ...
The_Moviemonster's user avatar

Only top scored, non community-wiki answers of a minimum length are eligible