12
votes
Accepted
Why is vivado so wasteful with its D-flipflop placement?
Has the placer violated space constraints? No.
Has the router violated timings constraints? Probably not, if it finished successfully.
In which case you have a good design.
If you reduced the size ...
- 171k
10
votes
Accepted
Clock Phase Shift Not Working on FPGA
When there is a 90° phase shift between two 5MHz clocks, that means there is a 50ns skew between them.
If you divide those two clocks by 5000000 using two instances of the same counter structure, you'...
- 1,718
9
votes
FPGA logic threshold - distinguishing a logic 0 and 1
The logic levels are shown in Table 8 of your referenced datasheet.
- 15.2k
8
votes
Accepted
How to declare a global variable in Verilog
You are asking the wrong question.
In Verilog simulation, every signal can be a global. For debugging, we need to be able to see and potentially modify everything.
In Verilog synthesis, nothing is a ...
- 8,715
7
votes
Accepted
Vivado constraints wizard suggests a lot of nonsense generated clocks
The following code in alu infers a latch:
...
- 8,761
6
votes
How are Vivado's projects directories structured?
Don't add the project itself to git; instead add some sort of script to generate the project and required IP cores. There are all sorts of issues you'll run in to if you commit the actual project, the ...
- 41.5k
6
votes
Implement glDrawArrays function in FPGA
This question shows a fundamental lack of understanding about how all these things relate, and is therefore unanswerable, except to explain why the question doesn't make sense. It's like you asked:
I ...
- 12.6k
6
votes
Vivado Simulation Running Very Slow
Welcome to the wonderful world of FPGA simulation. Yes, simulations take a long time. Running for a full second is a lot of simulation.
One trick you can do is speed up your blink rate just for the ...
- 3,144
6
votes
Accepted
Will FPGA synthesis tools ignore unused modules?
Unlike software where the compiler will sometimes keep code around that isn't actually called (particularly for things like libraries), this isn't the case for HDL designs. This is because HDL isn't &...
- 41.5k
5
votes
Vivado Simulation Running Very Slow
F = 200 MHz or T = 5 ns is the fastest clock in your design and it looks like you don't have any events in your design to be captured at 100 ps precision. You can run simulation with a precision of ...
- 11k
5
votes
Multiplication in VHDL by a fraction
In the testbench, there are numerous values listed for same simulated time.
From the language reference:
The delay values supported with the after clause do not cumulate, but all relate to the same ...
- 1,987
5
votes
What are the multiple drivers in this code?
You make assignments to count from 2 different always blocks. You must only make assignments to a signal from one ...
- 8,761
4
votes
Accepted
Will inout ports used only as in or out be optimized?
In all likelihood, yes, the inout will be optimised away.
In fact in almost all devices there are no internal tri-state buffers on routing, so ...
- 68.6k
4
votes
Accepted
How to map custom IP to the output pin on FPGA
Are they broken all the way out to your top-level design? If not, you have to define some external ports in your block diagram, and then assign them in your constraints (XDC) file. Otherwise, those ...
- 6,416
4
votes
Accepted
VHDL: Demultiplexing a signal to one of many outputs while driving unused outputs to '0'
The problem with your code is that an assignment of the form:
a <= (3 => '0', others => '1');
must use constants for the offsets being assigned (in this ...
- 2,027
4
votes
Accepted
how to pass parameter variable to module in verilog
Parameters are defined at synthesis time, you can't change them at run time based on signals. With that in mind, there are basically two options: either convert that parameter to a signal, or ...
- 41.5k
4
votes
Accepted
Verilog nested for loop not behaving as expected
You have problems with the Operator Precedence.
The comparison ( < ) has higher precedence then you EXOR operator ( ^ ).
...
- 14.5k
4
votes
Accepted
Inherent Pseudo-Randomness in modern FPGA design tools
TL;DR; The answer may depend on the synthesis tools, but most likely the answer is no unless you use randomised seeds.
Certainly for modern versions of Intel/Altera Quartus (since some time before 12....
- 68.6k
4
votes
Accepted
Passing input on one pin of FPGA straight out to another output pin for monitoring
Unconstrain the output (set a false path) and the timing violation will go away.
In Vivado you put these in the .xdc file for your design. More about that here: https://forums.xilinx.com/t5/Timing-...
- 55.9k
4
votes
VHDL Synthesis Warnings
As BrianDrummond pointed out in the comment section, I was driving the same pins in my source file multiple times. Although this is only in simulation as it is during the test phase, and not on a FPGA ...
- 1,563
4
votes
Accepted
wrong output of a multiplier in IP catalogue
The value of 0xFFF on the output is correct.
Multiplying 0x001 and 0xFF6 as 12 Bit signed integers results in 0xFFFFF6.
Now you specify the output width as 12 Bit - and the uppermost 12 Bit of the ...
- 3,104
4
votes
Will FPGA synthesis tools ignore unused modules?
Vivado has a specific property top that you can use to set the top-level module. From there, the elaboration process looks recursively down the hierarchy collecting ...
- 8,715
4
votes
Accepted
How to transfer Vivado projects properly between PCs?
Today we tried a lot and found some ways to fix it.
First of all it seems like it occurs because Vivado tries to delete or overwrite old synthesis Data, which it could not be located because the paths ...
4
votes
Accepted
BASYS3 FPGA pin planning and configuration question
You need a constraints file which properly specify the voltage of the pins used in the design. Grab the BASYS3 board XDC file. Copy that into your project (add it as a source) and un-comment all of ...
- 168
4
votes
Accepted
Is there any chance to configure DDR3L SDRAM on Digilent Arty A7 FPGA development board to Dual Channel memory?
No.
Multi-channel memory requires completely independent memory ICs and buses.
The Arty fails simply because there is only a single memory IC.
If there are multiple ICs, there are three possible ...
- 12.7k
4
votes
Accepted
Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?
If you want the design input signals to be synchronous to the clock, you need to drive them from the testbench in a similar manner as to how you drive them in the design, namely:
Using nonblocking ...
- 8,761
4
votes
Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?
A couple of issues.
Use only blocking assignments in making assignments to your clock; do not use nonblocking.
Waveforms do not always give you a good pitcure of exactly when assignments are made in ...
- 8,715
4
votes
Parsing Vivado reports
You'd script vivado using its Tcl interface. There, you get report_design_analysis, which can output things as CSV or JSON. Function Documentation, with you run ...
- 98.2k
Only top scored, non community-wiki answers of a minimum length are eligible