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Vivado and simulation for a 4-bit up counter

I figured out the problem in my codes. Insrtead of using +, I should have used | for or ...
user97662's user avatar
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Xilinx Virtex-7 VC709 FPGA Clock Setup Problem

When using PLLs/MMCMs with modern FPGA toolchains, the tools are generally smart enough to figure out all of the derived constraints. So you shouldn't need to specify any sort of generated clock ...
alex.forencich's user avatar
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D latch module in VHDL using NAND structure

What is the difference between a positive-level D latch and a negative-level D latch? Go from the words: The "positive-level D latch" latches the data when the level on the control/clock ...
Marcus Müller's user avatar

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