A message from our CEO about the future of Stack Overflow and Stack Exchange. Read now.

New answers tagged

0

First, FPGAs can't arbitrarily configure single transistors to do things such as making a tie. An ASIC designer can, but an ASIC is not an FPGA. "Why would HLS implement this array as a ROM and use resources instead of converting it to ties of VCCs and GNDs?" In your mind, what is constitutes a "ROM" bit in an FPGA? Is it a transistor pair in a ...


Top 50 recent answers are included