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3

You never initialized counter, so the simulator can't tell whether or not ready is being driven in the cntr process. This U state overrides the drive from the rst_pr process. Note that this is a problem only in the simulator. IRL (in real life), the counter will always have a definite value, even if you don't know what it is, and therefore, you'll know ...


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If you are only trying to implement your circuit then to me it seems that you are over thinking this: first let’s give NAME to the different signals: simulate this circuit – Schematic created using CircuitLab Now, let’s right the equations that rules the circuit: s_3 = s_1 XOR s_2 s_4 = NOT s_2 s_out = s_1 AND s_2 Now, let's write the ...


3

Don't use AudioClock as a clock for your component Transmitter : I2S_Transmitter instead use MCLK as the clock and AudioClock as a enable when you want action to take place. The way you did it is that you generated a new signal which will pretend that it is a clock signal, but it isn't. Look it up on the net to see how to generate a real clock, but hear I ...


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With Vivado you can do this one of four ways: Define the counter with HDL (uses fabric and LUTs) Instance a DSP48 with HDL Use block design Binary Counter, instance as 'fabric' Use block design Binary Counter, instance as 'DSP48' You can also define your own parameterized RTL blocks if you need something more exotic than that.


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My guess is it requires more than one clock to calculate ((l_count * 68) / 100000) + 1. There should be a warning about this in the synthesis/timing report. First thing that can be done is reduce the 68/100000 to 17/25000. The synthesizer should have done the same optimization. Then split the calculation across multiple clocks. Notice in the CatchEchoState ...


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The ILA grabs a single window of data for each trigger that it sees. So once the first one has happened, it will not collect any more data after the end of that window. If the second transaction does not come along within that window then you will not see it. If you set the number of windows to '2' (or more), you will see both transactions as connected to ...


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Ok, I figured out my stupid mistake, I changed the o_Tx to next_Tx in the nested case statement and it worked.


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