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49

Your classmate is wrongly treating the transistors in your circuit as magical devices whose behaviour is completely controlled by something that appears at the gate and only the gate. They are failing to see the transistor in your digital logic circuit as an actual transistor. MOSFETs don't react to ones and zeroes at the gate. They don't react to the ...


46

I spent some years in a startup commercialising async design technology, so I'm familiar with the reasons: async isn't intrinsically faster. The worst-case path delay remains the same. It's just that sometimes you get to take advantage of a faster path executing. async has overhead of completion detection too. Design tools. This is the really big one: there ...


28

In the logic gate level digital design abstraction, inputs are assumed to switch from logic HIGH to logic LOW and vice-versa instantaneously. This is done to simplify logic design. However, in the real world, it takes finite time to switch from one logic level to another. We want the time interval between switching from one logic level to another to be as ...


24

What is 180 degrees phase shift? When the signal is a sine wave, a 180 degrees phase shift delays the signal for half the period of that sine wave, the sine wave then looks inverted: Can an inverter do this? No, because it has signal gain, the output would be a square wave, not a sine. When the signal is a square wave with a 50% duty cycle, then something ...


15

Synthesizing means somehow converting what you have described (in Verilog here) into real hardware. Now in your Verilog you say that you have a 50ns delay. Ok, but now, in term of hardware, how would you convert this into actual hardware? If you are using an FPGA, how would you actually build your 50ns delay using the available FPGA resources (LUT, ...


12

The definition of chicken bit in Wiktionary is incorrect, and the extension by OP [as hardwired] is even more wrong. The chicken bit is a configuration bit (software configurable! and usually undocumented) that is incorporated into a design to disable a WORKAROUND of some issue discovered during bring-up of early silicon stepping. The bit is usually ...


11

Here is a (slightly dated) paper that discusses the differences: http://www.ece.neu.edu/faculty/ybk/publication/ASSESSING_MERDRAM_ELSEVIER.pdf Basically, it boils down to a few important differences. Leakage current. The pass transistors for the DRAM cells must be extremely low leakage, otherwise the leakage current will affect the bit stored in the ...


8

The N channel JFET needs a negative voltage on its gate with respect to source therefore this complicates the power supply regime by requiring the addition of a negative rail. Similarly, for a P channel device its gate would have to rise above Vcc to be able to control it. Here's an n channel JFET pictorially: - As you can see, the voltage on the gate has ...


8

In an unsigned binary representation, only positive numbers can be represented, and the weight of each bit including the most significant bit is a power of two. So with a word size of 8 (byte), 00000000 => 0 01111111 => 127 10000000 => 128 11111111 => 255 Two's-complement, which is used for signed binary notation, encodes both positive and ...


8

The assertion timing doesn't matter because the whole point is that all the elements of the circuit enter a valid/known reset state. It generally doesn't matter what order they do it in, only that the final state is predictable. De-assertion is a problem because if some flip-flops come out of reset before others, they may start changing state while others ...


7

The resistance of a resistor is proportional to it's length, and resistivity, and inversely proportional to it's width. The smallest (cheapest) way to make, on silicon, a narrow isolated resistor with high resistivity, is to control the resistivity by controlling the number of electrons/holes, and to pinch the width of the resistor by applying an electric ...


7

So could anyone explain to me why an AND gate needs six transistors? An AND gate does not need 6 transistors - this is because you're specifically referring to FCMOS (Fully Complementary MOS) where a PDN and PUN are completely complementary, as proven formally through De Morgan's laws. It can actually be shown there's no way to implement a NAND with just 1 ...


6

Porting my answer from SO. Which focuses on why it is impractical to synthesise absolute delays When synthesising clock trees the synthesis tool balances these by adding delays so that all nodes receive the clock at the same time, so it would seem that the synthesis tool does have the ability to add delays. However when ASICs are manufactured there is a ...


6

We don't just answer homework for you here. First, do you understand what setup and hold times mean? If not, look those up. One way to solve this is to draw a timing diagram with CLK transitioning from low to high at T=0. Now work thru the delays to make the CLK signal as seen by the flip flop, then show the range of time over which the D input to the ...


6

In 2's complement the MSb is defined as -(2n) where n is the bit position of the MSb. Due to how numbers work, all bits other than the MSb add up to (2n)-1. Adding those together results in -1.


6

This is standard technique and quite a good way to subtract voltages, as long as they are static/slow moving. You use analog switches to first connect your capacitor between V1 and V2, now VCAP = V1-V2. Then you switch the capacitor to ground. Now you have V1-V2 referenced to ground. C2 holds the voltage on the output, while the capacitor is sampling. It ...


5

http://en.m.wikipedia.org/wiki/Copper_interconnect provides some answers: aluminium was easier to deposit; a new process had to be developed for copper. copper ruins silicon's semiconductor behaviour if it leaks into it, so part of the process development is sealing to keep out the copper. the conductivity benefit isn't as big as you might think. However, ...


5

The technology file contains the physical properties of your fabrication process. For example, it would contain the number of metal layers, the design rules, resistances, capacitances, as well as the routing grid needed. This file is specific to the process used, so it would be supplied by the foundry or your gate library vendor. If there are multiple ...


5

I have seen VDDIO supply is more than VDDCore. This is required, as the smallest transistors (and other structures) in modern chip technology cannot support higher voltages than VDDCore limits. These structures are so tiny that they would break when supplied with VDDIO. But you need these tiny transistors in the core because they are the "fastest" and ...


5

Large integrated circuits usually have multiple power planes to meet the requirements of different parts of the circuitry on the chip. Splitting core and I/O supplies onto separate rails is quite common. This is done so that the core can be built with smaller transistors that offer the best possible performance characteristics (higher density, smaller ...


5

Standard cells usually refer to blocks of logic that are arranged into a library of elements. This is the library you buy from a fabrication facility (FAB) when you order their cervices for chip fabrication. These "cells" are coming fully validated and characterized by the vendor for each particular fabrication node, with all timing and power consumption etc....


5

Or (this depends a bit on the application and so on) use a differential amp. Can the two voltages share the same reference? simulate this circuit – Schematic created using CircuitLab You might need buffering, and the time constants could be tweaked, but you get the idea.


5

Here's a quick (and to me, easy to understand) answer, no equations needed. Others have pointed out that Vgs is what controls nmos on/off state. If you try to use nmos as a pull-up element, the nfet ends up raising its own source voltage. If source voltage goes up, current goes down. It turns itself off! This happens before the voltage reaches the supply. It ...


4

Routing or PNR takes the longest time as they have to match the timing. It usually finishes the last as they are the recipient of all the chip blocks (typically from various departments). Once all the blocks are received they make sure that the blocks are placed optimally so that the timing is met. The team also generates huge data (~700GB in my case per ...


4

Consider the circuit diagram in which a CMOS inverter drives a capacitive load. The delay offered by the inverter is the time taken to charge/discharge the capacitor and is defined as \$\tau = (t_{LH} + t_{HL})/2\$. Where \$t_{LH}\$ is the time required to charge the capacitor. This happens via pMOS transistor and \$t_{LH} = C_{L}R_{p}\$. Similarly, \$t_{HL}...


4

SET forces the output (Q) high and the inverse output low. CLR "clears" the flip-flop, meaning the output is forced low and the inverse output high. The SET and CLR inputs are asynchronous to the clock, meaning they work at any time, not just on a clock edge as the D input does.


4

They certainly can be. The problem is that they're not very well behaved. They are only used where absolutely necessary. For low frequencies, they're pretty much out of the question as they would be too large. For RF, they are used regularly to build filters and baluns and what not. However, inductors built with planar processes have lots of nasty ...


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