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Why would an AND gate need six transistors?

Your classmate is wrongly treating the transistors in your circuit as magical devices whose behaviour is completely controlled by something that appears at the gate and only the gate. They are failing ...
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Why aren't fully asynchronous circuits more prevalent?

I spent some years in a startup commercialising async design technology, so I'm familiar with the reasons: async isn't intrinsically faster. The worst-case path delay remains the same. It's just that ...
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Why would an AND gate need six transistors?

In the logic gate level digital design abstraction, inputs are assumed to switch from logic HIGH to logic LOW and vice-versa instantaneously. This is done to simplify logic design. However, in the ...
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Can a NOT gate be used to achieve 180 degree phase shift?

What is 180 degrees phase shift? When the signal is a sine wave, a 180 degrees phase shift delays the signal for half the period of that sine wave, the sine wave then looks inverted: Can an inverter ...
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Why delays cannot be synthesized in Verilog?

Synthesizing means somehow converting what you have described (in Verilog here) into real hardware. Now in your Verilog you say that you have a 50ns delay. Ok, but now, in term of hardware, how would ...
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Why does decreasing the CMOS supply voltage also decrease the maximum circuit frequency?

Decreasing the voltage decreases the maximum frequency that can be used such that the operation of the digital system is as desired. This is because the equivalent resistance, $R_{eq}$, of the CMOS ...
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Precise differences between DRAM and CMOS processes

Here is a (slightly dated) paper that discusses the differences: http://www.ece.neu.edu/faculty/ybk/publication/ASSESSING_MERDRAM_ELSEVIER.pdf Basically, it boils down to a few important differences. ...
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Are chicken bits left in space-qualified ICs?

The definition of chicken bit in Wiktionary is incorrect, and the extension by OP [as hardwired] is even more wrong. The chicken bit is a configuration bit (software configurable! and usually ...
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How can I design a digital circuit where the output is 5 times the input?

If you draw out the truth table it becomes simple. You have two inputs so there are only four possible output values. In - Out ----------- 00 | 0000 01 | 0101 10 | 1010 11 | 1111 Now look down the ...
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Why are MOSFETs used for VLSI IC fabrication instead of JFETs?

The N channel JFET needs a negative voltage on its gate with respect to source therefore this complicates the power supply regime by requiring the addition of a negative rail. Similarly, for a P ...
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Why are 11, 111, 1111, ... equivalent to -1 in two's complement?

In an unsigned binary representation, only positive numbers can be represented, and the weight of each bit including the most significant bit is a power of two. So with a word size of 8 (byte), <...
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Why is de-assertion of an asychronous reset a problem compared to its assertion?

The assertion timing doesn't matter because the whole point is that all the elements of the circuit enter a valid/known reset state. It generally doesn't matter what order they do it in, only that ...
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Prevent spikes during transition of inputs in AND gate

There's nothing that can be done to eliminate output spikes in this circuit. The AND gate is suffering from an 'internal race condition'. This would often be referred to as a 'decoding spike', as they ...
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Why would an AND gate need six transistors?

So could anyone explain to me why an AND gate needs six transistors? An AND gate does not need 6 transistors - this is because you're specifically referring to FCMOS (Fully Complementary MOS) where a ...
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Why does lowering VDD increases the delay for digital circuits?

Most of these circuits are CMOS, particularly if they support a wide range of supply voltages. In a MOSFET, the higher the difference between the gate and source voltages, the higher the current that ...

How do processor transistor counts keep increasing, without geometric scaling?

For a given size chip area, the number of transistors on it continues to increase as the size of the transistor -the feature size - decreases. What that comment is implying is the node name, 5 nm for ...
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Why delays cannot be synthesized in Verilog?

Porting my answer from SO. Which focuses on why it is impractical to synthesise absolute delays When synthesising clock trees the synthesis tool balances these by adding delays so that all nodes ...
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How do I calculate the maximum frequency?

We don't just answer homework for you here. First, do you understand what setup and hold times mean? If not, look those up. One way to solve this is to draw a timing diagram with CLK transitioning ...
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Why are 11, 111, 1111, ... equivalent to -1 in two's complement?

In 2's complement the MSb is defined as -(2n) where n is the bit position of the MSb. Due to how numbers work, all bits other than the MSb add up to (2n)-1. Adding those together results in -1.

How to store the difference of 2 voltages on capacitor?

This is standard technique and quite a good way to subtract voltages, as long as they are static/slow moving. You use analog switches to first connect your capacitor between V1 and V2, now VCAP = V1-...
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Which software is used to design (and simulate) IC?

Digital design Digital circuit design is usually done using a HDL language like Verilog or VHDL. This can be simulated on digital level with tools like Modelsim / Questa. https://eda.sw.siemens.com/...
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Random clock Generation with unequal 1s and 0s distribution?

Think of the contents of the N-bit LFSR as an N-bit integer. This number will have a uniform distribution of values from 1 to 2N - 1. You can generate a variable density of mask bits by comparing this ...
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Why VDDIO is more than VDDcore supply in VLSI/ integrated chips?

I have seen VDDIO supply is more than VDDCore. This is required, as the smallest transistors (and other structures) in modern chip technology cannot support higher voltages than VDDCore limits. ...
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Why VDDIO is more than VDDcore supply in VLSI/ integrated chips?

Large integrated circuits usually have multiple power planes to meet the requirements of different parts of the circuitry on the chip. Splitting core and I/O supplies onto separate rails is quite ...
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What is standard about standard cells in layout designing?

Standard cells usually refer to blocks of logic that are arranged into a library of elements. This is the library you buy from a fabrication facility (FAB) when you order their cervices for chip ...
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