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2 votes

How to estimate timing contraints for FPGAs?

As your FPGA and micro-controller run of different clocks, there is NO timing relation between them. To safely transfer data between them you have to use synchronizers or a circuit which has clock ...
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Interfacing FPGA to an external chip and timing constraints

Basically what you're trying to do is create a delayed clock to capture your input, and thus allow more setup time for the return signals. While treating the return signals as 'source sync' with a ...
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Quartus II - Can I include other files into a *.qsf file?

Tested with Quartus II 15.0 Its possible to add lines like these to the *.qsf file: ...
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Creating multiple Ring oscillators and placing them through Hard macro

Well, the error messages are very clear: You're driving the same output signal with multiple drivers. And that's exactly what your code (and schematic) show: you're driving out2 with several ring ...
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1 vote

How should I translate old TIG statement from UCF to new Vivado XDC files?

set_false_path is not only for for internal paths. You can use set_false_path for The port from which all paths are to be set as false paths: ...
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Quartus II - Can I include other files into a *.qsf file?

In Quartus Prime ver. 18.1 it is possible to do: set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pinout.tcl
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Quartus II - Can I include other files into a *.qsf file?

Try these commands in the qsf file - set_global_assignment -name PRE_FLOW_SCRIPT_FILE quartus_sh:script_file.tcl For an example checkout this page - The example script file is in the zip archive ...
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