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21 votes
Accepted

Why doesn't this circuit work?

The cathode of the LED must be connected to the ground not Vcc
Paul Ghobril's user avatar
  • 2,906
16 votes
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Are FPGAs for experimentation alone?

I also read an article that they are used for testing purposes alone. That is so ridiculous that I think you misunderstood the article. FPGAs are used for various applications, including data ...
user1850479's user avatar
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15 votes
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What is a "half latch" in an FPGA?

A half-latch is a gate with positive feedback implemented with a weak pull-up transistor: simulate this circuit – Schematic created using CircuitLab When the input is actively driven, it ...
Dmitry Grigoryev's user avatar
12 votes

How is a signal physically routed in an FPGA?

Your interpretation is overly simplistic. Real FPGAs have a complex hierarchy of routing resources, some for local connections only, some for medium-range connections and some for spanning the entire ...
Dave Tweed's user avatar
  • 175k
12 votes
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FPGA: count up or count down?

Optimizing to this level will break your heart. The result could change because of the technology of the FPGA you're using, other factors in the FPGA, but also because of factors outside of your ...
pscheidler's user avatar
  • 1,079
10 votes
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Is this BRAM being fully utilized if I use a different data width?

Correct, the remaining bits are unused. This is something you just have to accept in FPGAs, you are never going to use all of the resources. It's the price you pay for configurability. On the plus ...
Tom Carpenter's user avatar
9 votes
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What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?

I think the differences can be boiled down into a few key points: First, boards that are designed for ASIC emulation can have several, very large FPGAs that usually provide mostly pure fabric logic ...
alex.forencich's user avatar
9 votes
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Clock jitter - ppm, ui, ps

The "Good News" first: I can save you using an online calculator. "ppm" is for "parts per million"; so 50 ppm simply means a relative error of 50·10⁻⁶; at 200 MHz, that ...
Marcus Müller's user avatar
9 votes

FPGA logic threshold - distinguishing a logic 0 and 1

The logic levels are shown in Table 8 of your referenced datasheet.
jonathanjo's user avatar
  • 14.9k
8 votes

Is this BRAM being fully utilized if I use a different data width?

In addition to Tom's answer: BlockRAMs have one additional (mostly called parity) bit per byte giving you: 9(8+1), 18(16+2), 36(32+4), 72(64+8) bits. These bits can be used for simple parity ...
Paebbels's user avatar
  • 3,957
8 votes
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Partially associated formal cannot have actual OPEN in VHDL under Vivado

In VHDL, you cannot connect an individual element of a port to open. You must connect either the whole port to open, or connect ...
scary_jeff's user avatar
  • 2,007
7 votes
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Why isn't this decoder being inferred as a LUT?

The RTL schematic shows you how it has interpreted your code. As you can see, it has the exact combination of AND gates and multiplexers that your code describes. ...
scary_jeff's user avatar
  • 2,007
7 votes

How to decrease used LUTs in FPGA Design?

Put your character data into BlockRAM instead of using LUTs as distributed RAM.
bobflux's user avatar
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7 votes
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What is the relationship between a 10:5 Gearbox and a 5:1 OSERDES2?

When converting parallel data to serial data, you take a parallel bus running at low frequency, and then clock it out serially at a much higher frequency. Why doesn't it use different type ...
Tom Carpenter's user avatar
7 votes
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Xilinx Spartan 3A programming connection : where are MISO and MOSI pins?

If you are expecting to be able to just use your programmer to load a configuration bitstream directly into the FPGA which only stores that in specialized SRAM, you are in for a surprise when it ...
DKNguyen's user avatar
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7 votes
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How to declare a global variable in Verilog

You are asking the wrong question. In Verilog simulation, every signal can be a global. For debugging, we need to be able to see and potentially modify everything. In Verilog synthesis, nothing is a ...
dave_59's user avatar
  • 8,630
6 votes

What is this multiplexer doing in this design?

It looks like it allows the output flip-flop to be triggered by either the rising or falling edge of K (the clock signal), as selected by how you configure the multiplexer.
kwc's user avatar
  • 511
6 votes
Accepted

Xilinx bit file different between builds

There is an option to randomize the build process, which IIRC is enabled by default. As FPGA layout is an optimization problem with high complexity, it is not possible to find the globally optimal ...
Simon Richter's user avatar
6 votes

External clock with Arty Z7 FPGA development board

If the frequency is low (which is usually the case for audio applications), generally what is done on FPGAs is to use clock enables. The idea is to detect the edges of the input signal with a fast ...
alex.forencich's user avatar
6 votes
Accepted

I2C communication not working

The voltage you see on your bus line corresponds to a resistance of the low side switch of something above 200 ohm. A quick glance in the schematic of the ZedBoard shows, that some input pins have a ...
jusaca's user avatar
  • 9,609
6 votes

How to store a configuration on an FPGA

The Nexys board use (like many FPGAs) an on-board serial flash to download its firmware from. The flash is connected to the FPGA with Quad SPI serial link. At startup the FPGA is the master of the SPI ...
PierreOlivier's user avatar
6 votes

Vivado Simulation Running Very Slow

Welcome to the wonderful world of FPGA simulation. Yes, simulations take a long time. Running for a full second is a lot of simulation. One trick you can do is speed up your blink rate just for the ...
td127's user avatar
  • 3,126
6 votes
Accepted

From Xilinx to Efinix - how to calculate the needed units?

it looks like Efinix is using a quite different design idea for the logical units. Yep, different slice designs is what typically sets FPGA series apart. How to calculate the needed elements in ...
Marcus Müller's user avatar
6 votes

Can glitches in hardware be eliminated completely by using behavioural code instead of structural gate-level implementations?

This may change the behaviour of the VHDL simulation, but when you actually want to operate the circuit in an FPGA, both of them are going to be turned into (probably) the same hardware with the same ...
Stack Exchange Supports Israel's user avatar
5 votes

Do I need a license to design IP cores with AXI interfaces?

The AMBA specification (which includes all of the AXI-3, AXI-4, ACP, AXI Stream protocol) is available for license from ARM for no cost. To get the license, you need to create an account at ARM.com (...
Mac's user avatar
  • 151
5 votes
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Including one module in another module with variable

You need to go back to basics. Verilog is a hardware description language, not a programming language. Your code is describing hardware. Let's see what your code is trying to infer: ...
Tom Carpenter's user avatar
5 votes

SPI interface on Xilinx FPGA, clock domains and timing constraints

The usual approach is to cross MOSI, CS and SCLK to the internal FPGA fabric clock (running at a far higher rate then the SPI bus) domain and do all the actual work there. Crossing a clock domain ...
Dan Mills's user avatar
  • 17.6k
5 votes

gcc __attribute__ section not working?

It turns out I wasn't using the gcc attribute correctly. I was trying to place the variable directly into OCM using: ...
pr871's user avatar
  • 1,167
5 votes

What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?

Boards for ASIC prototyping tend to be bigger FPGA devices with higher I/O counts, with I/O brought to headers, and almost no on board peripherals. FPGA eval platforms have somewhat smaller chips, ...
hacktastical's user avatar
  • 54.8k

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