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14

A half-latch is a gate with positive feedback implemented with a weak pull-up transistor: simulate this circuit – Schematic created using CircuitLab When the input is actively driven, it overrides the signal coming from the weak pullup. When the input is in Z-state, the weak pullup can keep the logical "1" at the input (and "0" at the output) ...


13

At a place I worked there were two camps of FPGA designers. One camp I called simulate, simulate, simulate or s cubed. The other camp was all about design. The s cubed guys used a simulator like modelsim, they would come up with an initial design via coding methods and\or blocks in the design suite. Then they would simulate it and find the things that ...


12

I haven't done this for double precision FP, but the same principles apply as for single precision, for which I have implemented division (as multiply by reciprocal). What these FPGAs do have, instead of FPUs, is hardwired DSP/multiplier blocks, capable of implementing a 18*18 or (Virtex-5) 18*25 multiplication in a single cycle. And the larger devices ...


12

Yes you can. There are some applications notes using the differential pairs inside an FPGA as a low cost ADC. There is a very good document describing this that you can use for your design: Analysis on Digital Implementation of Sigma-Delta ADC with Passive Analog Components


12

Your interpretation is overly simplistic. Real FPGAs have a complex hierarchy of routing resources, some for local connections only, some for medium-range connections and some for spanning the entire chip. These structures have been developed over many years of studying application designs, trying to strike a balance between the area required for routing ...


12

Optimizing to this level will break your heart. The result could change because of the technology of the FPGA you're using, other factors in the FPGA, but also because of factors outside of your control, including the fitter's random number seed. Having said that, I believe that option 3 will be the best. Options 1 and 2 have a comparator/OR gate going ...


11

If you multiply 2 5-bit numbers (A and B are both std_logic_vector(4 downto 0)) don't you need 10 bits (not 9) to store it in (so P should be std_logic_vector(9 downto 0)? (31*31 = 961: needs 10 bits) But also - don't use std_logic_arith/_unsigned. Use ieee.numeric_std and then use the unsigned data type.


11

There's no reason to use FPGAs unless you need to. Even two similarly talented engineers in the MCU and FPGA fields would use an MCU for a relatively simple automation task. Pro MCU: MCUs usually have all the peripherals to the outside world ready to go Compiling takes seconds (FPGAs take minutes to hours) There are an order of magnitude (or two!) more ...


11

Yes, it's because you are using the "silicon" oscillator. The basys2 board also provides a socket for a crystal oscillator. If you plug in a crystal oscillator and use its clock signal the jitter is gone and the VGA image will be fine. I have tried it myself. BTW: The manual tells you about that: The primary silicon oscillator is flexible and ...


10

If it is removing them, they are in fact unused, but it is not always obvious why. I think in your case, the reason is: .sample_in({8{sw}}), The synthesiser is clever enough to realise the bits in each word of your memories (smp_buf and vga_buf) are identical. As a result, it decides there is no point duplicating the hardware, it might as well just have a ...


8

I wonder if there is another way of looking at the problem? Playing off your estimation of 512 FFT operations (64 point each) and 42k MAC operations... I presume this is what you need for one pass through the algorithm? Now you have found an FFT core using 4 DSP units ... but how many clock cycles does it take per FFT? (throughput, not latency)? Let's say ...


8

I think the differences can be boiled down into a few key points: First, boards that are designed for ASIC emulation can have several, very large FPGAs that usually provide mostly pure fabric logic resources (as opposed to DSP slices, hard IP cores, and transceivers) with lots of interconnections between them vs. "normal" dev boards which usually have just ...


7

It would be better to use a vendor independent (and therefore portable) pure VHDL approach. Any good synthesis tool will infer a ROM from this code: case address is when 1 => result <= 14; when 2 => result <= 45; when 3 => result <= 67; when 4 => result <= 32; when 5 => result <= 12; ...


7

Assuming you need a read cycle on each port on each clock cycle, each BRAM will give you two read ports. Beyond that, you have to replicate the contents of the memory. Is the bandwidth required at each port less than the raw bandwidth of the BRAM? In that case, you might consider multiplexing the ports. Use a counter that runs at the full speed of the BRAM ...


7

The code you show is essentially a priority encoder. That is, it has an input of many signals, and its output indicates which of those signals is set, giving priority to the left-most set signal if more than one is set. However, I see conflicting definitions of the standard behavior for this circuit in the two places I checked. According to Wikipedia, the ...


7

The warning you are seeing is most likely WARNING:PhysDesignFules:2410 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer 39999. I just got this warning myself a couple of days ago and ...


7

Just because they use the same number of bits, doesn't mean that you can perform operations on them in the same way. Look at how a float is actually constructed internally - how the bits are used (sign, exponent, fraction) and then think about what would happen if you simply did integer operations on it.


7

Because this line: last_clk_val <= count_clk; is outside of the clocked process, both signals will have the same value in hardware (and also in simulation after a delta-cycle1). Thus, this condition within your process if (last_clk_val = '0' and count_clk = '1') then will never be true and the process will be equivalent to: process(clk, reset) begin ...


7

The RTL schematic shows you how it has interpreted your code. As you can see, it has the exact combination of AND gates and multiplexers that your code describes. If you want to know how it has mapped this into the FPGA resources, you need to look at the 'technology schematic'. Note that the technology schematic is hard to navigate unless you set the ...


7

Put your character data into BlockRAM instead of using LUTs as distributed RAM.


6

The .ppr file is the PlanAhead project file. Assuming the project is named project, it references these files which appear to be needed ./project.data/constrs_1/fileset.xml ./project.data/sources_1/fileset.xml ./project.data/runs/runs.xml ./project.data/runs/impl_1.psg runs.xml seems to also contain output/status information so changes onrecompile. impl_1....


6

The best way (depending on how complex your final design will be) would probably be to use a separate fast CMOS oscillator for your CPLD system clock, and have it process the input pulses and output the stepper pulse. This way, the clock is running all the time when the system is on, and it can time the period from the last input pulse - if it's above a ...


6

ThePhoton's answer is an excellent one. I would like to add some additional information here for your consideration. This stems from the fact that even though we have state of the art fancy FPGA and CPLD devices using HDLs and systhesis tools it can be informative to look closely at things designed years ago. Stay with me while I walk through this to my ...


6

The cat6a specifications are for 100m and 10Gb ethernet (so that's fine?) I think what you're trying to say with this is that if 10G Ethernet can transmit 100 m over Cat6A cable, then it should be possible to transmit 3.2 Gb/s over 50 m with the same cable. The difference between what it sounds like you want to do and how 10GbE does things is that the ...


6

In VHDL, if a port is declared "out", it can be assigned to, but it can't be used elsewhere inside the module. Specifically, the assignment on line 155 would be flagged as an error: OE <= RDA; Making the port "inout" makes this usage allowable. However, inout ports are "messy" for a number of reasons, and I try to avoid them wherever possible. Another ...


6

Xilinx create a YouTube video (sigh) to deal with this. Here is the link to the video http://www.xilinx.com/training/vivado/vivado-version-control-overview.htm Here is my summary of the video (8 minutes) Before you start If you really like full control, Xilinx suggests that you forgo the GUI entirely and do everything on the command line, and then you ...


6

FPGA manufacturers don't use equivalent gate counts much any more, even in the hand-wavyest marketing materials. Like lines of code or megahertz of processor speed, it's a highly inaccurate metric for measuring the device capability, and in the FPGA markets the customers wised up enough to suppress its use. To estimate the size device you need, you'll need ...


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