Hot answers tagged

21 votes
Accepted

Why doesn't this circuit work?

The cathode of the LED must be connected to the ground not Vcc
user avatar
  • 2,567
16 votes
Accepted

Are FPGAs for experimentation alone?

I also read an article that they are used for testing purposes alone. That is so ridiculous that I think you misunderstood the article. FPGAs are used for various applications, including data ...
user avatar
  • 10.4k
15 votes

How to get a FPGA design that will definitely work on actual hardware

At a place I worked there were two camps of FPGA designers. One camp I called simulate, simulate, simulate or s cubed. The other camp was all about design. The s cubed guys used a simulator like ...
user avatar
  • 63.3k
14 votes
Accepted

What is a "half latch" in an FPGA?

A half-latch is a gate with positive feedback implemented with a weak pull-up transistor: simulate this circuit – Schematic created using CircuitLab When the input is actively driven, it ...
user avatar
12 votes

How is a signal physically routed in an FPGA?

Your interpretation is overly simplistic. Real FPGAs have a complex hierarchy of routing resources, some for local connections only, some for medium-range connections and some for spanning the entire ...
user avatar
  • 164k
12 votes
Accepted

FPGA: count up or count down?

Optimizing to this level will break your heart. The result could change because of the technology of the FPGA you're using, other factors in the FPGA, but also because of factors outside of your ...
user avatar
  • 1,049
10 votes
Accepted

having distorted image in VGA with FPGA board

Yes, it's because you are using the "silicon" oscillator. The basys2 board also provides a socket for a crystal oscillator. If you plug in a crystal oscillator and use its clock signal the jitter is ...
user avatar
  • 15.7k
10 votes
Accepted

Vivado is removing registers which will be used

If it is removing them, they are in fact unused, but it is not always obvious why. I think in your case, the reason is: .sample_in({8{sw}}), The synthesiser is ...
user avatar
9 votes
Accepted

What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?

I think the differences can be boiled down into a few key points: First, boards that are designed for ASIC emulation can have several, very large FPGAs that usually provide mostly pure fabric logic ...
user avatar
8 votes
Accepted

Clock jitter - ppm, ui, ps

The "Good News" first: I can save you using an online calculator. "ppm" is for "parts per million"; so 50 ppm simply means a relative error of 50·10⁻⁶; at 200 MHz, that ...
user avatar
7 votes
Accepted

Xilinx bitgen warning

The warning you are seeing is most likely ...
user avatar
7 votes
Accepted

FPGA Floating-point to Unsigned 32bits

Just because they use the same number of bits, doesn't mean that you can perform operations on them in the same way. Look at how a float is actually constructed internally - how the bits are used (...
user avatar
  • 13.2k
7 votes
Accepted

Xilinx ISE warns that a signal is trimmed since it has a constant value of 0, but the signal is used within my code

Because this line: last_clk_val <= count_clk; is outside of the clocked process, both signals will have the same value in hardware (and also in simulation ...
user avatar
  • 1,256
7 votes
Accepted

Why isn't this decoder being inferred as a LUT?

The RTL schematic shows you how it has interpreted your code. As you can see, it has the exact combination of AND gates and multiplexers that your code describes. ...
user avatar
  • 1,937
7 votes

How to decrease used LUTs in FPGA Design?

Put your character data into BlockRAM instead of using LUTs as distributed RAM.
user avatar
  • 57.6k
7 votes
Accepted

Partially associated formal cannot have actual OPEN in VHDL under Vivado

In VHDL, you cannot connect an individual element of a port to open. You must connect either the whole port to open, or connect ...
user avatar
  • 1,937
7 votes
Accepted

What is the relationship between a 10:5 Gearbox and a 5:1 OSERDES2?

When converting parallel data to serial data, you take a parallel bus running at low frequency, and then clock it out serially at a much higher frequency. Why doesn't it use different type ...
user avatar
7 votes
Accepted

Xilinx Spartan 3A programming connection : where are MISO and MOSI pins?

If you are expecting to be able to just use your programmer to load a configuration bitstream directly into the FPGA which only stores that in specialized SRAM, you are in for a surprise when it ...
user avatar
  • 46.3k
6 votes
Accepted

Using SVN with Xilinx Vivado?

Xilinx create a YouTube video (sigh) to deal with this. Here is the link to the video http://www.xilinx.com/training/vivado/vivado-version-control-overview.htm Here is my summary of the video (8 ...
user avatar
6 votes
Accepted

Can program FPGA but not PROM on my Spartan-3A dev board

You've got the wrong device. In order to program the SPI Flash using the indirect JTAG method, you need to right click on the FPGA and select Add BPI/SPI Flash. It'...
user avatar
  • 5,334
6 votes
Accepted

Which is the best way to version control Xilinx PlanAhead projects?

My personal workflow (I mention planAhead, but vivado is similar), with goal to add as little as possible to source-control: Files exist outside the planAhead project directory. Take care since if ...
user avatar
6 votes
Accepted

What could be the usage of material declaration datasheet for Spartan-6 package?

The materials declaration is used if your product needs to comply with RoHS or other regulatory restrictions on material content. RoHS not only requires that your product not contain certain ...
user avatar
  • 121k
6 votes
Accepted

Pulse on edge of different clock

Your second implementation fails because of what is a common mistake. The code pattern: ...
user avatar
  • 1,937
6 votes

How to get a FPGA design that will definitely work on actual hardware

Main things are: Careful coding to avoid non-synthesizable structures Minimize logic levels for better timing performance (make logic between registers as simple as possible) test, test, test to ...
user avatar
6 votes
Accepted

Dual port RAM on Altera and Xilinx FPGA

I've also now just tried compiling for a Stratix V with Quartus 15.0 which does have M20K blocks, and you are correct - it infers two M20Ks which should not be the case. In fact using the Verilog test ...
user avatar
6 votes
Accepted

Is this BRAM being fully utilized if I use a different data width?

Correct, the remaining bits are unused. This is something you just have to accept in FPGAs, you are never going to use all of the resources. It's the price you pay for configurability. On the plus ...
user avatar
6 votes

Is this BRAM being fully utilized if I use a different data width?

In addition to Tom's answer: BlockRAMs have one additional (mostly called parity) bit per byte giving you: 9(8+1), 18(16+2), 36(32+4), 72(64+8) bits. These bits can be used for simple parity ...
user avatar
  • 3,797
6 votes

What is this multiplexer doing in this design?

It looks like it allows the output flip-flop to be triggered by either the rising or falling edge of K (the clock signal), as selected by how you configure the multiplexer.
user avatar
  • 471
6 votes
Accepted

Xilinx bit file different between builds

There is an option to randomize the build process, which IIRC is enabled by default. As FPGA layout is an optimization problem with high complexity, it is not possible to find the globally optimal ...
user avatar
6 votes

External clock with Arty Z7 FPGA development board

If the frequency is low (which is usually the case for audio applications), generally what is done on FPGAs is to use clock enables. The idea is to detect the edges of the input signal with a fast ...
user avatar

Only top scored, non community-wiki answers of a minimum length are eligible