At a place I worked there were two camps of FPGA designers. One camp I called simulate, simulate, simulate or s cubed. The other camp was all about design.
The s cubed guys used a simulator like modelsim, they would come up with an initial design via coding methods and\or blocks in the design suite. Then they would simulate it and find the things that ...
A half-latch is a gate with positive feedback implemented with a weak pull-up transistor:
simulate this circuit – Schematic created using CircuitLab
When the input is actively driven, it overrides the signal coming from the weak pullup. When the input is in Z-state, the weak pullup can keep the logical "1" at the input (and "0" at the output) ...
I also read an article that they are used for testing purposes alone.
That is so ridiculous that I think you misunderstood the article. FPGAs are used for various applications, including data processing in specialized applications, and as glue logic in low volume applications where developing a fixed function ASIC would not be viable. Open up all kinds of ...
Yes you can. There are some applications notes using the differential pairs inside an FPGA as a low cost ADC.
There is a very good document describing this that you can use for your design:
Analysis on Digital Implementation of Sigma-Delta ADC with
Passive Analog Components
Your interpretation is overly simplistic. Real FPGAs have a complex hierarchy of routing resources, some for local connections only, some for medium-range connections and some for spanning the entire chip. These structures have been developed over many years of studying application designs, trying to strike a balance between the area required for routing ...
Optimizing to this level will break your heart. The result could change because of the technology of the FPGA you're using, other factors in the FPGA, but also because of factors outside of your control, including the fitter's random number seed.
Having said that, I believe that option 3 will be the best. Options 1 and 2 have a comparator/OR gate going ...
Yes, it's because you are using the "silicon" oscillator.
The basys2 board also provides a socket for a crystal oscillator.
If you plug in a crystal oscillator and use its clock signal the jitter is gone and the VGA image will be fine. I have tried it myself.
BTW: The manual tells you about that:
The primary silicon oscillator is flexible and
If it is removing them, they are in fact unused, but it is not always obvious why.
I think in your case, the reason is:
The synthesiser is clever enough to realise the bits in each word of your memories (smp_buf and vga_buf) are identical. As a result, it decides there is no point duplicating the hardware, it might as well just have a ...
I think the differences can be boiled down into a few key points: First, boards that are designed for ASIC emulation can have several, very large FPGAs that usually provide mostly pure fabric logic resources (as opposed to DSP slices, hard IP cores, and transceivers) with lots of interconnections between them vs. "normal" dev boards which usually have just ...
The "Good News" first: I can save you using an online calculator.
"ppm" is for "parts per million"; so 50 ppm simply means a relative error of 50·10⁻⁶; at 200 MHz, that means 200·10⁶ Hz · 50·10⁻⁶ = 10000 Hz. It's that simple!
Doesn't have anything to do with jitter.
Your clock could be running at, say 200.010 MHz (...
The warning you are seeing is most likely
WARNING:PhysDesignFules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and default,
may be incorrect and should not be used. For more information, please
reference Xilinx Answer 39999.
I just got this warning myself a couple of days ago and ...
Just because they use the same number of bits, doesn't mean that you can perform operations on them in the same way.
Look at how a float is actually constructed internally - how the bits are used (sign, exponent, fraction) and then think about what would happen if you simply did integer operations on it.
Because this line:
last_clk_val <= count_clk;
is outside of the clocked process, both signals will have the same value in hardware (and also in simulation after a delta-cycle1). Thus, this condition within your process
if (last_clk_val = '0' and count_clk = '1') then
will never be true and the process will be equivalent to:
The RTL schematic shows you how it has interpreted your code. As you can see, it has the exact combination of AND gates and multiplexers that your code describes. If you want to know how it has mapped this into the FPGA resources, you need to look at the 'technology schematic'.
Note that the technology schematic is hard to navigate unless you set the ...
In VHDL, you cannot connect an individual element of a port to open. You must connect either the whole port to open, or connect some elements to your intended signals, and others to 'dummy' unused signals.
So you have a couple of options:
Q8 => open, -- Just associate the whole port with `open`
if for some reason you must use individual association:
When converting parallel data to serial data, you take a parallel bus running at low frequency, and then clock it out serially at a much higher frequency.
Why doesn't it use different type modesules such as 10:1 Gear box ...?
A "gearbox" is basically nothing more than a SERDES block, the only difference being that the output is typically multi-bit wide. ...
Xilinx create a YouTube video (sigh) to deal with this. Here is the link to the video
Here is my summary of the video (8 minutes)
Before you start
If you really like full control, Xilinx suggests that you forgo the GUI entirely and do everything on the command line, and then you ...
FPGA manufacturers don't use equivalent gate counts much any more, even in the hand-wavyest marketing materials. Like lines of code or megahertz of processor speed, it's a highly inaccurate metric for measuring the device capability, and in the FPGA markets the customers wised up enough to suppress its use.
To estimate the size device you need, you'll need ...
I'll preface this with the caveat that I'm not that up to date on the interior workings of recent FPGA architectures. So this answer may not be appropos. depending upon whether the FPGA tools support the design flow I will discuss.
It's probably true the total volume of raw gates shipped into the market are probably latch based designs. This is because of ...
You've got the wrong device.
In order to program the SPI Flash using the indirect JTAG method, you need to right click on the FPGA and select Add BPI/SPI Flash. It'll ask for the device type and your programming files. The type should be SPI Flash M25P16 according to this document, page 106. Then highlight the SPI Flash you just added and select the Program ...
My personal workflow (I mention planAhead, but vivado is similar), with goal to add as little as possible to source-control:
Files exist outside the planAhead project directory. Take care since if you use the GUI to add/create files, it will likely be inside the project directory.
IP cores exists in my source directories, one sub-folder by IP core.
The materials declaration is used if your product needs to comply with RoHS or other regulatory restrictions on material content.
RoHS not only requires that your product not contain certain materials, but also that you document this fact. Typically, in order to do that, you need to request the vendors of all the components in your design to provide a ...
Your second implementation fails because of what is a common mistake. The code pattern:
if rising_edge(clk_a) then
signal_a <= '1';
elsif falling_edge(clk_b) then
signal_a <= '0';
Cannot be realised in hardware, because it describes a 1-bit register with two different clock inputs. Such a register does not exist in the FPGA fabric; ...
Main things are:
Careful coding to avoid non-synthesizable structures
Minimize logic levels for better timing performance (make logic between registers as simple as possible)
test, test, test to ensure functional correctness and check for things like uninitialized regs and disconnected wires
synthesis and check synthesis logs for warnings, make sure the ...
I've also now just tried compiling for a Stratix V with Quartus 15.0 which does have M20K blocks, and you are correct - it infers two M20Ks which should not be the case. In fact using the Verilog test code I have just removed from my answer also infers two M20Ks.
Why? The True Dual-Port Requirements
A single-port RAM of the size you are interested in ...
Correct, the remaining bits are unused.
This is something you just have to accept in FPGAs, you are never going to use all of the resources. It's the price you pay for configurability.
On the plus side, if at a later date you decide to add something like parity information or just make the data bus a little wider, you can do that essentially for free as ...
In addition to Tom's answer:
BlockRAMs have one additional (mostly called parity) bit per byte giving you:
These bits can be used for simple parity algorithms to "secure" your data. Or you can implement ECC. You can also store meta information like Valid, StartOfFrame/EndOfFrame in these additional bits. ...