21
votes
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16
votes
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Are FPGAs for experimentation alone?
I also read an article that they are used for testing purposes alone.
That is so ridiculous that I think you misunderstood the article. FPGAs are used for various applications, including data ...
- 16k
15
votes
How to get a FPGA design that will definitely work on actual hardware
At a place I worked there were two camps of FPGA designers. One camp I called simulate, simulate, simulate or s cubed. The other camp was all about design.
The s cubed guys used a simulator like ...
- 78k
15
votes
Accepted
What is a "half latch" in an FPGA?
A half-latch is a gate with positive feedback implemented with a weak pull-up transistor:
simulate this circuit – Schematic created using CircuitLab
When the input is actively driven, it ...
- 25.7k
12
votes
How is a signal physically routed in an FPGA?
Your interpretation is overly simplistic. Real FPGAs have a complex hierarchy of routing resources, some for local connections only, some for medium-range connections and some for spanning the entire ...
- 170k
12
votes
Accepted
FPGA: count up or count down?
Optimizing to this level will break your heart. The result could change because of the technology of the FPGA you're using, other factors in the FPGA, but also because of factors outside of your ...
- 1,079
10
votes
Accepted
Vivado is removing registers which will be used
If it is removing them, they are in fact unused, but it is not always obvious why.
I think in your case, the reason is:
.sample_in({8{sw}}),
The synthesiser is ...
- 64.7k
9
votes
Accepted
What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?
I think the differences can be boiled down into a few key points: First, boards that are designed for ASIC emulation can have several, very large FPGAs that usually provide mostly pure fabric logic ...
- 40.8k
9
votes
FPGA logic threshold - distinguishing a logic 0 and 1
The logic levels are shown in Table 8 of your referenced datasheet.
- 13.2k
8
votes
Accepted
Is this BRAM being fully utilized if I use a different data width?
Correct, the remaining bits are unused.
This is something you just have to accept in FPGAs, you are never going to use all of the resources. It's the price you pay for configurability.
On the plus ...
- 64.7k
8
votes
Is this BRAM being fully utilized if I use a different data width?
In addition to Tom's answer:
BlockRAMs have one additional (mostly called parity) bit per byte giving you:
9(8+1),
18(16+2),
36(32+4),
72(64+8) bits.
These bits can be used for simple parity ...
- 3,907
8
votes
Accepted
Clock jitter - ppm, ui, ps
The "Good News" first: I can save you using an online calculator.
"ppm" is for "parts per million"; so 50 ppm simply means a relative error of 50·10⁻⁶; at 200 MHz, that ...
- 90.4k
7
votes
Accepted
Xilinx ISE warns that a signal is trimmed since it has a constant value of 0, but the signal is used within my code
Because this line:
last_clk_val <= count_clk;
is outside of the clocked process, both signals will have the same value in hardware (and also in simulation ...
- 1,286
7
votes
Accepted
Why isn't this decoder being inferred as a LUT?
The RTL schematic shows you how it has interpreted your code. As you can see, it has the exact combination of AND gates and multiplexers that your code describes. ...
- 1,977
7
votes
How to decrease used LUTs in FPGA Design?
Put your character data into BlockRAM instead of using LUTs as distributed RAM.
- 72k
7
votes
Accepted
Partially associated formal cannot have actual OPEN in VHDL under Vivado
In VHDL, you cannot connect an individual element of a port to open. You must connect either the whole port to open, or connect ...
- 1,977
7
votes
Accepted
What is the relationship between a 10:5 Gearbox and a 5:1 OSERDES2?
When converting parallel data to serial data, you take a parallel bus running at low frequency, and then clock it out serially at a much higher frequency.
Why doesn't it use different type ...
- 64.7k
7
votes
Accepted
Xilinx Spartan 3A programming connection : where are MISO and MOSI pins?
If you are expecting to be able to just use your programmer to load a configuration bitstream directly into the FPGA which only stores that in specialized SRAM, you are in for a surprise when it ...
- 55.4k
6
votes
Accepted
Pulse on edge of different clock
Your second implementation fails because of what is a common mistake. The code pattern:
...
- 1,977
6
votes
How to get a FPGA design that will definitely work on actual hardware
Main things are:
Careful coding to avoid non-synthesizable structures
Minimize logic levels for better timing performance (make logic between registers as simple as possible)
test, test, test to ...
- 40.8k
6
votes
Accepted
Dual port RAM on Altera and Xilinx FPGA
I've also now just tried compiling for a Stratix V with Quartus 15.0 which does have M20K blocks, and you are correct - it infers two M20Ks which should not be the case. In fact using the Verilog test ...
- 64.7k
6
votes
What is this multiplexer doing in this design?
It looks like it allows the output flip-flop to be triggered by either the rising or falling edge of K (the clock signal), as selected by how you configure the multiplexer.
- 511
6
votes
Accepted
Xilinx bit file different between builds
There is an option to randomize the build process, which IIRC is enabled by default.
As FPGA layout is an optimization problem with high complexity, it is not possible to find the globally optimal ...
- 12.4k
6
votes
External clock with Arty Z7 FPGA development board
If the frequency is low (which is usually the case for audio applications), generally what is done on FPGAs is to use clock enables. The idea is to detect the edges of the input signal with a fast ...
- 40.8k
6
votes
Accepted
I2C communication not working
The voltage you see on your bus line corresponds to a resistance of the low side switch of something above 200 ohm.
A quick glance in the schematic of the ZedBoard shows, that some input pins have a ...
- 9,404
6
votes
How to store a configuration on an FPGA
The Nexys board use (like many FPGAs) an on-board serial flash to download its firmware from. The flash is connected to the FPGA with Quad SPI serial link.
At startup the FPGA is the master of the SPI ...
- 622
6
votes
Accepted
How to declare a global variable in Verilog
You are asking the wrong question.
In Verilog simulation, every signal can be a global. For debugging, we need to be able to see and potentially modify everything.
In Verilog synthesis, nothing is a ...
- 7,812
6
votes
Vivado Simulation Running Very Slow
Welcome to the wonderful world of FPGA simulation. Yes, simulations take a long time. Running for a full second is a lot of simulation.
One trick you can do is speed up your blink rate just for the ...
- 2,967
6
votes
Can glitches in hardware be eliminated completely by using behavioural code instead of structural gate-level implementations?
This may change the behaviour of the VHDL simulation, but when you actually want to operate the circuit in an FPGA, both of them are going to be turned into (probably) the same hardware with the same ...
- 12.1k
Only top scored, non community-wiki answers of a minimum length are eligible