The L1 latency is a question for Xilinx since it depends on the implementation, or you can measure it as referenced in this question.
For a general overview of the L1 memory system, you can check the TRM. There is a 64 bit instruction datapath, which means a limit of 2 instructions fetched per cycle. Decode is also limited to 2 per cycle. Dispatch width ...
This is not a ring oscillator, because r0 is unknown. You probably meant r_out:
Also see: rout vs r_out.
If you correct your topology, you will run into another problem: a timing (delta) loop, basically a correct ring oscillator without delays will hang your simulator at 0 time. You will have to introduce a delay in your "mynot" ...
Yes, the processor subsystem (PS) boots before the programmable logic (PL) is configured. Chapter 6 of the Zynq-7000 SoC Technical Reference Manaul covers this topic in some detail.
The only way to bypass this sequence is to configure the PL directly through its hardware JTAG interface.
The simplest (in fact standard) solution is to have an 'enable' signal in the logic which stops everything when low.
Then you have a register with this enable signal, which you write high from the CPU.
Thus nothing runs until YOU tell it to.
This also solves the problems if the processor is slow to start.
Nowadays it may take a long time before a ...
I think the differences can be boiled down into a few key points: First, boards that are designed for ASIC emulation can have several, very large FPGAs that usually provide mostly pure fabric logic resources (as opposed to DSP slices, hard IP cores, and transceivers) with lots of interconnections between them vs. "normal" dev boards which usually have just ...
Boards for ASIC prototyping tend to be bigger FPGA devices with higher I/O counts, with I/O brought to headers, and almost no on board peripherals.
FPGA eval platforms have somewhat smaller chips, fewer I/O headers and more built-in peripherals like DDR, Ethernet, HDMI, and so forth.
With Vivado you can do this one of four ways:
Define the counter with HDL (uses fabric and LUTs)
Instance a DSP48 with HDL
Use block design Binary Counter, instance as 'fabric'
Use block design Binary Counter, instance as 'DSP48'
You can also define your own parameterized RTL blocks if you need something more exotic than that.
The ILA grabs a single window of data for each trigger that it sees. So once the first one has happened, it will not collect any more data after the end of that window. If the second transaction does not come along within that window then you will not see it.
If you set the number of windows to '2' (or more), you will see both transactions as connected to ...