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That clock input is supposed to be synchronous with the LVDS data, so inserting a PLL like that does not make any sense. Not to mention it's not possible as drawn as the IBUFDS_DIFF_OUT instance is an input buffer and as such may only be connected directly to the appropriate IO pins on the FPGA. This is because those instances are physically located in the ...


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Thank you fellas for your insights. Turns out, registering the SPI CLK is what got it done. I first had to bring back the FPGA clock as an input, then created a one-bit register 'sclk_r', then a new 'always' block which registered the wire input 'sclk' with the new register 'sclk_r'. The 'Pi SPI clock is about 1MHz. So, the FPGA is oversampling it at 50:1 ...


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I'm not sure if this is your problem, but I don't think you are handling the increment of count correctly. This variable can have exactly 8 values (in hardware) and you use all 8 of those values. So, there is no need to explicitly reset count when it reaches 111...just increment it and let it roll over to zero. I am also suspicious of the logic that you use....


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