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4

Are they broken all the way out to your top-level design? If not, you have to define some external ports in your block diagram, and then assign them in your constraints (XDC) file. Otherwise, those pins will remain internal / not-connected. Right-click in the BD, and create a port (Ctrl+K): Then, when you auto-generate the wrapper for the block diagram, ...


4

It turns out I wasn't using the gcc attribute correctly. I was trying to place the variable directly into OCM using: volatile u32 x __attribute__ ((section ("psu_ocm_ram_0_MEM_0"))) = 10; as if the compiler is able to put individual variables into specific memory locations. Rather, it's the linker that's responsible for assigning all executable code (data ...


3

Yes, the processor subsystem (PS) boots before the programmable logic (PL) is configured. Chapter 6 of the Zynq-7000 SoC Technical Reference Manaul covers this topic in some detail. The only way to bypass this sequence is to configure the PL directly through its hardware JTAG interface.


3

The problem of processing a 2-d kernel of data over a large dataset (not just convolution) comes up so regularly in HD video processing that I came up with a generic way of handling it that I use all the time. I developed a generic "kernel generator" that uses line buffers and registers to present all of the input data for a given output pixel in parallel. ...


3

Since this was originally posted I have ditched this ADI-based design for one based off the TRD. For anyone with a similar problem, I found a correct build of the ADI reference design here (same as Steven's link but his was broken for me), and it requires custom drivers found here. But it is worth noting that I switched my approach because the ADI design ...


3

Trace length equalization for a differential pair is not determined by setup/hold timing. It is determined by having a crossover point of eye diagram in right place, to keep it in the middle. The allowable timing skew therefore depends on reasonable slew rate of signal edges. As I understand, the camera max frequency is 720 mbps, or 1380 ps of unit interval....


2

Can you be more specific about what you want to do with these arrays? Are you outputting them to the terminal? What is it that you are trying to accomplish with your design? Is it something that could be done with a processor only or are you using the FPGA for a specific hardware algorithm? Have you read the Xilinx documentation or seen the Vivado ...


2

Consider this: If you are trying to use the 0x72 address as a 7-bit entity then you need to be able to see 0xE4 on the scope as the first I2C byte coming out on SDA. Since you are only seeing 0x64 it means that you are not operating the I2C interface controller (or software if bit banging). The loss of the intended upper bit has nothing to do with whether ...


2

Put in a memory interface in the FPGA logic and then strap an external RAM chip onto the side of the FPGA. Using static RAM (SRAM) for this is the easiest to implement. If you need a nonvolatile solution use a FRAM chip that has a parallel interface.


2

It is not stated in ADV7511W Programming Guide PDF that the address which is given is in 8-bit format, so if you're using Zynq7002 you need to write address of slave in 7-bit format to I2C peripheral address register, which is 0x72 >> 1 = 0x39 (PD/AD is pulled down to the ground with the 10k resistor). Before transfer initiating byte is sent, value (0x39) ...


2

Looks like there is a path but you should read the docs to be sure. From the Xilinx docs The PL can be configured and reconfigured by PS software in secure or non-secure mode. The PCAP path is the most commonly deployed method as it does not require that the PL be pre-programmed with a bitstream. The PL can also be configured by the TAP controller on ...


2

A FPGA is a set of programmable logic gates made to excel in one thing, and one thing only. A CPU is a set of fixed logic gates made to be used for a large variety of purposes. If you decide to use the FPGA for something, you better be using it often. Otherwise you're carrying idle logic. This is why a CPU is often more cost effective. When you're not ...


1

It appears to be an industry standard thing, yes: see this PDF. For each clock period at the pixel clock rate, you have to transmit seven bits on each LVDS channel. Keen observers will spot that 4*7 is actually 28 rather than 24; the other four bits seem to be used for sync.


1

The issue is that the keywords "posedge" and "negedge" in Verilog (or "rising_edge" and "falling_edge" in VHDL) have very special meaning to the synthesizer. The synthesizer gives every signal attached with these keywords a dedicated clock routing network on the FPGA. Do not use those keywords for any signal that you do not want connected to a clock routing ...


1

I'm having a tough time finding higher gauge wire that specifies a characteristic impedance and I don't feel like putting two lengths of 100 ohm ethernet cable in parallel to make a single connection. Cat 5 cable is 100 ohms differential, which is exactly what you want. Your prototypical coaxial solution uses two 50-ohm cables for the two arms of a ...


1

With Xilinx devices, using an ODDR is actually the recommended way to output a clock signal on a pin, especially if you have tight timing constraints. Do this for both clk and clk180, and both will have the same, repeatable timing. It is not a workaround at all. See comment on the Xilinx forum here by a Xilinx Engineer: ODDR keeps the duty cycle and ...


1

It shouldn't be necessary to connect the CLK125 line to anything on the Zynq7020. We have had success in our implementation just leaving it as a no-connect on the PHY. See also Sheet 6 of the Zedboard Schematics where they do something similar. Zedboard Schematics


1

A device can fail anytime, and drivers have to handle such problems gracefully. So, don't oops and and don't run into endless loops. Instead, report an error code to userspace or upstream device driver. (This usually isn't a problem unless a device has VM-mapped RAM or doing DMA transfers.) The purpose of the device tree is to take the knowledge of ...


1

This question is basically about the nature of compilation, hardware vs software, and the speed of light (not kidding!) Compilation (as in, what gcc does) is exploiting constants to improve the performance of your program. The cpu type is a constant, therefore the program can be compiled to machine code instead of being interpreted on a virtual machine. ...


1

From my experience, most of the I2C addresses are given in 7-bit format, unless it is explicitly stated otherwise (in such a case they would say explicitly, "... for reading use the address 0xYY and for writing use the address 0xZZ..."). But as Michael Karas said in his answer, what you see with the oscilloscope has absolutely nothing to do with how the ...


1

That means exactly what you wrote: if you need to supply some external clock to the chip, you use input clock; the processor clock is used to run processor; the DDR clock is used to communicate with external DDR memory, and the PL clock can be used to supply the programmable logic on the chip. Check this UG585 user guide chapter 25. EDIT: (a response to ...


1

I don't know that particular board, but there is more then you ever want to know about the clocking on the 7 series parts here: http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf Basically you can run a single ended clock into the thing (Subject to picking an appropriate IO standard), but there are constraints to watch out ...


1

It seems that Xilinx code works as long as the XScuGic is not reinitialized in different place. In other words you need to initialize & use xInterruptController: extern XScuGic xInterruptController; int main() { XScuGic_Config *scuGicConfig = XScuGic_LookupConfig(0); XScuGic_CfgInitialize(&xInterruptController, scuGicConfig, scuGicConfig-&...


1

Assuming this is a Cortex-A9 Zynq 7000, you will find documentation on how to use interrupts with FreeRTOS on the following link: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html - with worked examples in the official FreeRTOS download. Information on locating the example within the official FreeRTOS download can be found on the ...


1

You should be able to use your design tools to check what the synthesizer has done with mem. Check the RTL schematic first, and make sure it looks 'sane' (i.e. make sure mem appears as some form of RAM). The RTL schematic shows you the non-architecture specific synthesized HDL. Then check the "Technology Schematic" (I think that's what Xilinx calls it, at ...


1

What you have to do is package sub modules as IP. Then you can use the IP as sub modules in a bigger design. The problem is that you can only package a whole block diagram. What you have to do is create a new block diagram, insert the blocks making a sub-module, package it as an IP and then add it to the main design. Repeat for all sub modules. Created IPs ...


1

The interconnect between the Processing System and Programmable Logic is limited by the bus width of the AXI interface. It sound like you are looking for a way of passing a buffer directly from software to the PL all in one go, rather than individual write operations. If this is the case I would suggest looking into using the Direct Memory Access (DMA) IPs ...


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