Electrical Engineering
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ironstein's user avatar
ironstein's user avatar
ironstein
  • Member for 7 years, 3 months
  • Last seen more than 2 years ago
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About

I am an engineering student living in India.

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Top posts
All Questions Answers
Score Newest
question
9
How to get a FPGA design that will definitely work on actual hardware
Mar 2, 2016
question
6
Blocking vs Non Blocking Assignments
Mar 15, 2016
question
3
How to debug FPGA designs
Mar 12, 2016
question
2
Different ways of using DSP slices in Spartan 6 FPGA
Mar 6, 2016
question
2
What is traffic generator (while using Xilinx Memory Interface Generator)
Mar 7, 2016
question
2
Two different ways of writing the same thing but generating different behaviours in Verilog
Mar 17, 2016
answer
2
Why edge triggering is preferred over level triggering?
Mar 13, 2016
question
1
how to understand xilinx RTL schematics [closed]
Mar 1, 2016
question
1
How to debug combinational loop warning in Xilinx ISE
Mar 3, 2016
answer
-1
Lenient MUX and Load Signal
Feb 18, 2016
Top network posts
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9
Python Documentation (:obj:`str`) vs (str)
8
Writing Unit Tests for inherited classes in Java
5
using a C extension in python, without installing it as a module
5
How do I implement the Probability density function of a Gaussian Distribution

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