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Dr. Ehsan Ali's user avatar
Dr. Ehsan Ali's user avatar
Dr. Ehsan Ali's user avatar
Dr. Ehsan Ali
  • Member for 8 years, 2 months
  • Last seen more than a month ago
9 votes
4 answers
1k views

What method do you suggest for prototyping asynchronous circuits?

6 votes
3 answers
4k views

How do you design a CMOS buffer with exact same delay of a CMOS inverter?

6 votes
1 answer
12k views

Why Cadence not revealing their prices for their software product? [closed]

5 votes
1 answer
8k views

What is the standard way to halt a VHDL testbench after a certain time period?

4 votes
3 answers
2k views

What is a weak transistor?

4 votes
3 answers
14k views

How to make LTSpice sub-circuits available globally?

3 votes
2 answers
2k views

How to get a CMOS transistor SPICE model?

3 votes
1 answer
497 views

How to latch on very short digital pulses?

3 votes
2 answers
206 views

Multi level logic in transistor level. Possible?

2 votes
2 answers
1k views

Metastability simulation

2 votes
3 answers
1k views

How to implement a Muller C-element in a LUT4 of a FPGA?

1 vote
1 answer
391 views

How to accomplish parameterized subcircuits in LTSpice?

1 vote
2 answers
743 views

Which CMOS SPICE model should I choose?

1 vote
4 answers
4k views

What's the standard way to detect a digital signal transition?

1 vote
2 answers
685 views

Can you explain how the 2-phase dual rail channel works?

1 vote
0 answers
3k views

Implement a 3-input function using only two 2-input LUTs

1 vote
2 answers
2k views

How to define VHDL entity with two architectures?

1 vote
0 answers
124 views

VHDL bizarre behavior

1 vote
1 answer
2k views

What is the exact type of oil used in immersion cooling of electronic devices such as processors?

0 votes
1 answer
258 views

How to run Xilinx ISim simulater faster?

0 votes
1 answer
3k views

Set the threshold voltage of CMOS inverter to VDD/2 for both rising and falling edge: possible?

0 votes
3 answers
643 views

VHDL case with different outputs

0 votes
2 answers
104 views

How to view the optimized combinational function after HDL synthesis?

0 votes
1 answer
287 views

CMOS 4000 series postfix meaning: BCL, BCP, BD

0 votes
1 answer
797 views

Should I use NMOS or PMOS in CMOS demultiplexer circuit?

0 votes
2 answers
652 views

Dual edge triggered D flip flip CMOS implementation. Less than 20 transistors

0 votes
2 answers
80 views

Do we have a material that reshapes itself depending on applied voltage or electromagnetic field?

0 votes
1 answer
1k views

What is AO222 based design in concept of design of CMOS cell library?