Electrical Engineering
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Tim's user avatar
Tim's user avatar
Tim
  • Member for 11 years, 2 months
  • Last seen more than 6 years ago
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About

Professional ASIC engineer with experience in RTL design, Verilog, synthesis, power, and timing issues on billion+ gate ICs.

Other hobbies include:

  • Computer Graphics
  • Android Programming
  • C++ Programming

Personal released projects:

Portfolio Map-----------Electron Flux

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Top posts
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All Questions Answers
Score Newest
answer
11
Difference between @* and @(*) in Verilog
Mar 27, 2013
answer
8
Preference of NAND & NOR gates
Jun 15, 2013
answer
7
How are LFSRs used in real applications as PRNGs?
Jan 22, 2013
answer
7
Why is S=1, R=1 state forbidden in RS flip flop?
Mar 27, 2013
answer
7
Fixing Setup and hold timing violations in FPGA's and ASIC designs
Jun 20, 2013
answer
7
Accessing RAM instance from multiple modules in Verilog
Aug 19, 2013
answer
5
What are the general steps used in creating a ASIC?
Mar 8, 2013
answer
5
Concurrent assignment or output port connection should be a net type
Aug 25, 2013
question
4
Do 2 5V DC wall warts in the same AC outlet have a common DC ground?
Apr 12, 2013
answer
4
What can go wrong when producing an ASIC from an FPGA-verified verilog design?
Apr 18, 2013
Top Meta posts
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CircuitLab plugin doesn't load for me in latest Firefox
3
Time limit before edits commit to revision history
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160
Is there a command in Vim/Vi to move the cursor to the end of a search highlight?
73
Is glm::ortho() actually wrong?
59
How to find replace using regex groups in vim
59
set the texture for by glUniform1i
50
Why FloatBuffer instead of float[]?

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