User Tim

11 votes

Difference between @* and @(*) in Verilog

answered Mar 27, 2013 at 23:17

8 votes

Accepted

Preference of NAND & NOR gates

answered Jun 15, 2013 at 2:37

7 votes

Accepted

Fixing Setup and hold timing violations in FPGA's and ASIC designs

answered Jun 20, 2013 at 23:03

7 votes

Accessing RAM instance from multiple modules in Verilog

answered Aug 19, 2013 at 22:07

7 votes

Why is S=1, R=1 state forbidden in RS flip flop?

answered Mar 27, 2013 at 0:54

7 votes

How are LFSRs used in real applications as PRNGs?

answered Jan 22, 2013 at 3:07

5 votes

What are the general steps used in creating a ASIC?

answered Mar 8, 2013 at 22:37

5 votes

Accepted

Concurrent assignment or output port connection should be a net type

answered Aug 25, 2013 at 14:04

4 votes

What can go wrong when producing an ASIC from an FPGA-verified verilog design?

answered Apr 18, 2013 at 16:11

3 votes

Accepted

In verilog, what effect does the not (!) operator have on high impedance and don't care conditions?

answered May 2, 2013 at 4:41

3 votes

Shared parameter for several modules (Verilog)

answered Aug 19, 2013 at 15:38

3 votes

Verilog output port is high impedance (Z) when driven by a sub module

answered Mar 12, 2013 at 20:34

3 votes

Accepted

CMax: (New in circuits)

answered Mar 29, 2013 at 17:15

3 votes

Verilog Netlist format with "\"

answered Apr 3, 2013 at 22:14

2 votes

Accepted

Where to get 12V from my computer?

answered Mar 29, 2013 at 17:53

2 votes

Identifying Pins of an Unknown LCD

answered Aug 14, 2012 at 4:02

2 votes

What do square brackets represent in verilog?

answered Feb 22, 2013 at 21:23

2 votes

Signal is missing in the sensitivity list and expression truncation

answered Oct 7, 2013 at 3:51

2 votes

Static power of Xilinx FPGA

answered Apr 18, 2013 at 21:08

2 votes

Accepted

Parallel to less parallel without throttling

answered Jul 14, 2013 at 18:30

2 votes

Logic Circuits Vs Transistor Power Circuits

answered May 7, 2013 at 4:27

2 votes

What is important in computer clocks' signal: signal edges or intervals when signal is stable? Will multiple value propagation occur?

answered May 16, 2013 at 15:07

1 vote

Square law device using FPGA

answered May 1, 2013 at 16:19

1 vote

Arduino multiplexing help needed.

answered May 2, 2013 at 22:40

1 vote

Most efficient way to select between 10 large buses?

answered May 6, 2013 at 6:53

1 vote

QuestaSim/ModelSim simulation gives me unkown value in wave window. However I get them as X and x, what is the difference between the two?

answered Oct 28, 2013 at 16:33

1 vote

How to give a 2-D array as output of a function in Verilog?

answered Mar 12, 2013 at 7:07

1 vote

Altera DE1 seven segment display

answered Mar 16, 2013 at 5:08

1 vote

What does non-combinational area represent in synopsys design compiler

answered Mar 20, 2013 at 4:28

1 vote

Accepted

Can I dynamically change the input clock frequency of the AT91SAM3X8E?

answered Mar 26, 2013 at 17:54

Stack Exchange Network

35 Answers

Difference between @* and @(*) in Verilog

Preference of NAND & NOR gates

Fixing Setup and hold timing violations in FPGA's and ASIC designs

Accessing RAM instance from multiple modules in Verilog

Why is S=1, R=1 state forbidden in RS flip flop?

How are LFSRs used in real applications as PRNGs?

What are the general steps used in creating a ASIC?

Concurrent assignment or output port connection should be a net type

What can go wrong when producing an ASIC from an FPGA-verified verilog design?

In verilog, what effect does the not (!) operator have on high impedance and don't care conditions?

Shared parameter for several modules (Verilog)

Verilog output port is high impedance (Z) when driven by a sub module

CMax: (New in circuits)

Verilog Netlist format with "\"

Where to get 12V from my computer?

Identifying Pins of an Unknown LCD

What do square brackets represent in verilog?

Signal is missing in the sensitivity list and expression truncation

Static power of Xilinx FPGA

Parallel to less parallel without throttling

Logic Circuits Vs Transistor Power Circuits

What is important in computer clocks' signal: signal edges or intervals when signal is stable? Will multiple value propagation occur?

Square law device using FPGA

Arduino multiplexing help needed.

Most efficient way to select between 10 large buses?

QuestaSim/ModelSim simulation gives me unkown value in wave window. However I get them as X and x, what is the difference between the two?

How to give a 2-D array as output of a function in Verilog?

Altera DE1 seven segment display

What does non-combinational area represent in synopsys design compiler

Can I dynamically change the input clock frequency of the AT91SAM3X8E?