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Nipo
  • Member for 6 years, 5 months
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11 votes

DIY USB-C Coupler with two receptacles

10 votes
Accepted

Clock Phase Shift Not Working on FPGA

8 votes

How does JTAG program an MCU

7 votes
Accepted

SWDAP vs CMSIS-DAP vs DAPLink

4 votes
Accepted

How to easily resize strings in VHDL?

4 votes

Are USB type C pull resistor neccesary on CC and SBU pins?

4 votes

Converting a full-size USB-B port to USB-C

4 votes
Accepted

USB-C Debug Accessory Mode and USB 2.0

3 votes

Bootloader and Vector Table on STM32F051

3 votes
Accepted

On board 13.56MHz RFID antenna design

2 votes

Difference between RFCOMM and L2CAP Protocol in Bluetooth Communication

2 votes

WS2811 timing issue

2 votes
Accepted

How to wire USB-C connector?

2 votes
Accepted

Why is BSDL syntax so wordy?

2 votes
Accepted

What is the value that captured into BYPASS register?

2 votes
Accepted

Generate 10MHz clock in Artix-7 FPGA series

2 votes
Accepted

Does VHDL 2008 have built in function to convert std_logic_vector to character type?

1 vote

Reverse engineering: Why is there a PD IC in this Adapter?

1 vote
Accepted

Can I multiplex only VTREF for multiple SWD programmations?

1 vote

Type C to type C USB2.0

1 vote
Accepted

Why do the JTAG parallel registers update on the falling edge?

1 vote
Accepted

jtag boundary scan pin testing

1 vote

Where does the bit come from when capture the bits to scan cell in jtag Capture-DR stage?

1 vote

JTAG ID to differentiate similar devices

1 vote

VHDL FIFO w/ RAM

1 vote

Fiber-optic transceiver ICs for applications other than fiber-optic Ethernet?

1 vote

MAC Address as Serial Number in Embedded Systems

1 vote
Accepted

What stage is used to shift out TDO in JTAG?

1 vote

How BLE central determine the connection interval

0 votes
Accepted

TDO unable to capture MSB of Shifted data in JTAG