Electrical Engineering
Profile Activity
Network profile
807
reputation
3
13
23

nurabha

Apparently, this user prefers to keep an air of mystery about them.

4
answers
21
questions
~225k
people reached
  • Member for 8 years, 7 months
  • 126 profile views
  • Last seen Feb 18 at 18:56

Communities (29)

Top network posts

Top tags (48)

Score 2
Posts 2
Posts % 8
Score 1
Posts 9
Score 1
Posts 4
Score 1
Posts 3
Score 1
Posts 2
Score 0
Posts 10
View all tags →

Top posts (25)

All Questions Answers
Votes Newest
11 Difference between If-else and Case statement in VHDL Jun 19 '13
9 How is a VHDL variable synthesized by synthesis tools Jun 19 '13
8 Why FPGA's have latches when they are almost never used? Sep 2 '13
7 How to choose between Mealy and Moore state machine Jun 19 '13
5 How can the number of clock cycles required to complete an instruction in a pipelined processor less than pipeline latency? Sep 26 '13
4 Problem in writing register maps using C structure for a TI Microcontroller Oct 25 '14
4 Gated clocks and clock enables in FPGA and ASICS Jun 19 '13
4 Fixing Setup and hold timing violations in FPGA's and ASIC designs Jun 20 '13
2 Functional and Timing accuracy of an RTL Model Nov 24 '14
2 What is the meaning of “do not populate test points” in a board schematic Jul 19 '19
View all questions and answers →

Badges (39)

Gold

3

Rarest

Silver

13

Rarest

Bronze

23

Rarest

View all badges →