Electrical Engineering
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nurabha
  • Member for 9 years, 11 months
  • Last seen more than a month ago
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All Questions Answers
Score Newest
question
11
Difference between If-else and Case statement in VHDL
Jun 19, 2013
question
11
Why FPGA's have latches when they are almost never used?
Sep 2, 2013
question
10
How is a VHDL variable synthesized by synthesis tools
Jun 19, 2013
question
9
How to choose between Mealy and Moore state machine
Jun 19, 2013
question
5
How can the number of clock cycles required to complete an instruction in a pipelined processor less than pipeline latency?
Sep 26, 2013
question
4
Problem in writing register maps using C structure for a TI Microcontroller
Oct 25, 2014
question
4
Gated clocks and clock enables in FPGA and ASICS
Jun 19, 2013
question
4
Fixing Setup and hold timing violations in FPGA's and ASIC designs
Jun 20, 2013
question
2
Functional and Timing accuracy of an RTL Model
Nov 24, 2014
question
2
What is the meaning of "do not populate test points" in a board schematic
Jul 19, 2019
Top network posts
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16
Size of C++ classes
7
How to do arithmetic right shift in python for signed and unsigned values
7
Command \AtBeginEnvironment already defined
6
What is the fastest algorithm to find an element with highest frequency in an array
5
Increasing per thread register usage in CUDA

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