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5 votes

3 answers

6k views

How do you cast an integer as a time in VHDL?

asked Oct 3, 2018 at 19:22

2 votes

2 answers

342 views

What circuit performance changes may be caused by conformal coating?

asked Aug 16, 2018 at 13:13

2 votes

1 answer

229 views

Does DCMI mean dc mA?

asked Oct 31, 2017 at 18:33

2 votes

2 answers

1k views

Why do manufacturers strongly discourage using X7R capacitors in AC signal and mains filtering applications?

asked Apr 4, 2018 at 18:03

2 votes

4 answers

8k views

On a relay coil, why use an MOV instead of flyback diode?

asked Apr 10, 2018 at 13:39

2 votes

1 answer

739 views

Ethernet PHY TX & RX pin failures

asked Jun 18, 2018 at 18:57

1 vote

1 answer

194 views

What information does one need to size inrush current limiting resistors?

asked Jul 17, 2018 at 20:50

1 vote

0 answers

129 views

Are there commonly used equations for short-term overpower of wirewound resistors?

asked Aug 1, 2018 at 15:03

1 vote

0 answers

149 views

Where do hi-pot multipliers come from?

asked Apr 6, 2018 at 20:14

1 vote

2 answers

842 views

How fast do tantalum capacitors self-heal? [closed]

asked Feb 21, 2018 at 21:45

1 vote

1 answer

339 views

Is there an industry-wide name for anti-parallel diodes across an IGBT module's collector and emitter?

asked Oct 12, 2018 at 19:46

1 vote

2 answers

778 views

Is there a preferred order VHDL case/when and rising/falling_edge statements in processes?

asked Nov 8, 2018 at 20:30

1 vote

1 answer

1k views

Are horizontal and vertical back porches required for digital video, and if so, why?

asked Jan 9, 2019 at 18:18

1 vote

2 answers

660 views

How can I estimate TL431 output voltage swings based on datasheet alone?

asked Feb 13, 2019 at 16:15

1 vote

2 answers

4k views

Are Verilog if blocks executed sequentially or concurrently?

asked Jul 5, 2019 at 18:41

0 votes

1 answer

483 views

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

asked Jul 15, 2019 at 12:58

0 votes

1 answer

276 views

Do front and back porches for digtal video really matter?

asked Sep 10, 2019 at 19:42

0 votes

2 answers

612 views

Syntax and/or best practice for buffering a vector in Verilog or VHDL

asked Dec 3, 2019 at 18:05

0 votes

0 answers

135 views

What would cause streaking in graphics LCD display?

asked Jan 16, 2020 at 20:45

0 votes

1 answer

136 views

Performance changes to metal can transistors installed 40 years ago

asked Feb 25, 2020 at 19:16

0 votes

0 answers

25 views

Labeling requirements for equipment using off-the-shelf 900 MHz ISM radio

asked May 26, 2020 at 13:22

0 votes

0 answers

279 views

IGBT SOA rating vs. Short Circuit rating

asked Oct 4, 2017 at 19:39

0 votes

0 answers

185 views

How does one change Vivado IP signal types?

asked May 22, 2019 at 16:28

0 votes

1 answer

432 views

Why is 7:1 video serialization required?

asked May 28, 2019 at 14:01

0 votes

1 answer

207 views

How does a rocking arm voltage regulator work?

asked Oct 22, 2018 at 12:25

0 votes

1 answer

291 views

How are processes evaluated in VHDL if a signal appears/does not appear in a sensitivity list and a nested IF statement?

asked Sep 18, 2018 at 17:52

0 votes

1 answer

3k views

How do I override generic values in a VHDL testbench?

asked Sep 28, 2018 at 15:45

0 votes

2 answers

103 views

Are D flipflop inputs and clock thresholds the same for a given logic family?

asked Apr 2, 2018 at 20:41

0 votes

2 answers

423 views

Ethernet transformer saturation at low frequencies

asked Jul 12, 2018 at 16:25

Stack Exchange Network

29 Questions

How do you cast an integer as a time in VHDL?

What circuit performance changes may be caused by conformal coating?

Does DCMI mean dc mA?

Why do manufacturers strongly discourage using X7R capacitors in AC signal and mains filtering applications?

On a relay coil, why use an MOV instead of flyback diode?

Ethernet PHY TX & RX pin failures

What information does one need to size inrush current limiting resistors?

Are there commonly used equations for short-term overpower of wirewound resistors?

Where do hi-pot multipliers come from?

How fast do tantalum capacitors self-heal? [closed]

Is there an industry-wide name for anti-parallel diodes across an IGBT module's collector and emitter?

Is there a preferred order VHDL case/when and rising/falling_edge statements in processes?

Are horizontal and vertical back porches required for digital video, and if so, why?

How can I estimate TL431 output voltage swings based on datasheet alone?

Are Verilog if blocks executed sequentially or concurrently?

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

Do front and back porches for digtal video really matter?

Syntax and/or best practice for buffering a vector in Verilog or VHDL

What would cause streaking in graphics LCD display?

Performance changes to metal can transistors installed 40 years ago

Labeling requirements for equipment using off-the-shelf 900 MHz ISM radio

IGBT SOA rating vs. Short Circuit rating

How does one change Vivado IP signal types?

Why is 7:1 video serialization required?

How does a rocking arm voltage regulator work?

How are processes evaluated in VHDL if a signal appears/does not appear in a sensitivity list and a nested IF statement?

How do I override generic values in a VHDL testbench?

Are D flipflop inputs and clock thresholds the same for a given logic family?

Ethernet transformer saturation at low frequencies