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Bort
  • Member for 5 years, 8 months
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5 votes
3 answers
5k views

How do you cast an integer as a time in VHDL?

2 votes
2 answers
245 views

What circuit performance changes may be caused by conformal coating?

2 votes
1 answer
220 views

Does DCMI mean dc mA?

2 votes
2 answers
943 views

Why do manufacturers strongly discourage using X7R capacitors in AC signal and mains filtering applications?

2 votes
4 answers
6k views

On a relay coil, why use an MOV instead of flyback diode?

2 votes
1 answer
555 views

Ethernet PHY TX & RX pin failures

1 vote
1 answer
190 views

What information does one need to size inrush current limiting resistors?

1 vote
0 answers
122 views

Are there commonly used equations for short-term overpower of wirewound resistors?

1 vote
0 answers
84 views

Where do hi-pot multipliers come from?

1 vote
2 answers
745 views

How fast do tantalum capacitors self-heal? [closed]

1 vote
1 answer
243 views

Is there an industry-wide name for anti-parallel diodes across an IGBT module's collector and emitter?

1 vote
2 answers
622 views

Is there a preferred order VHDL case/when and rising/falling_edge statements in processes?

1 vote
2 answers
462 views

How can I estimate TL431 output voltage swings based on datasheet alone?

1 vote
2 answers
3k views

Are Verilog if blocks executed sequentially or concurrently?

0 votes
1 answer
341 views

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

0 votes
1 answer
169 views

Do front and back porches for digtal video really matter?

0 votes
2 answers
296 views

Syntax and/or best practice for buffering a vector in Verilog or VHDL

0 votes
0 answers
102 views

What would cause streaking in graphics LCD display?

0 votes
1 answer
130 views

Performance changes to metal can transistors installed 40 years ago

0 votes
0 answers
23 views

Labeling requirements for equipment using off-the-shelf 900 MHz ISM radio

0 votes
0 answers
256 views

IGBT SOA rating vs. Short Circuit rating

0 votes
0 answers
141 views

How does one change Vivado IP signal types?

0 votes
1 answer
272 views

Why is 7:1 video serialization required?

0 votes
1 answer
836 views

Are horizontal and vertical back porches required for digital video, and if so, why?

0 votes
1 answer
168 views

How does a rocking arm voltage regulator work?

0 votes
1 answer
216 views

How are processes evaluated in VHDL if a signal appears/does not appear in a sensitivity list and a nested IF statement?

0 votes
1 answer
3k views

How do I override generic values in a VHDL testbench?

0 votes
2 answers
81 views

Are D flipflop inputs and clock thresholds the same for a given logic family?

0 votes
2 answers
311 views

Ethernet transformer saturation at low frequencies